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參數(shù)資料
| 型號： | RV5C386A-E2 |
| 廠商： | RICOH COMPANY LTD |
| 元件分類： | XO, clock |
| 英文描述： | I2C-bus Real-Time Clock ICs with Voltage Monitoring Function |
| 中文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO10 |
| 封裝： | 4 X 2.90 MM, 1.20 MM HEIGHT, SSOP-10 |
| 文件頁數(shù)： | 33/42頁 |
| 文件大?。?/td> | 362K |
| 代理商： | RV5C386A-E2 |
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PRELIMINARY RV5C386A
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The alarm function can be set by presetting desired alarm time in the alarm registers (the Alarm_W Registers
for the day-of-week digit settings and both the Alarm_W Registers and the Alarm_D Registers for the hour
and minute digit settings) with the WALE and DALE bits once set to 0 and then to 1 in the Control Register 1.
Note that the WALE and DALE bits should be once set to 0 in order to disable the alarm interrupt circuit upon
the coincidental occurrence of a match between current time and preset alarm time in the process of setting
the alarm function.
current time =
preset alarm time
WALE
←
1
(DALE)
WALE
←
0
(DALE)
Interval (1min.) during which a match
between current time and preset alarm time
occurs
current time =
preset alarm time
WAFG
←
0
(DAFG)
Max.61.1
μ
s
/INTRB
(/INTRA)
WALE
←
1
(DALE)
WALE
←
1
(DALE)
current time =
preset alarm time
WALE
←
0
(DALE)
current time =
preset alarm time
/INTRB
(/INTRA)
14.4.2.
Periodic Interrupt
Setting of the periodic selection bits (CT2 to CT0) enables periodic interrupt to the CPU. There are two
waveform modes: pulse mode and level mode. In the pulse mode, the output has a waveform duty cycle of
around 50%. In the level mode, the output is cyclically driven low and, when the CTFG bit is set to 0, the
output is return to High (OFF).
Description
Interrupt Cycle and Falling Timing
OFF(H)
Fixed at “L”
2Hz(Duty50%)
1Hz(Duty50%)
Once per 1 second (Synchronized with
Second counter increment)
Once per 1 minute (at 00 seconds of every
Minute)
Once per hour (at 00 minutes and 00
Seconds of every hour)
Once per month (at 00 hours, 00 minutes,
and 00 seconds of first day of every month)
CT2
CT1
CT0
Wave form mode
-
-
Pulse Mode *1)
Pulse Mode *1)
Level Mode *2)
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
(Default)
1
0
1
Level Mode *2)
1
1
0
Level Mode *2)
1
1
1
Level Mode *2)
*1) Pulse Mode: 2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the second
counter as illustrated in the timing chart below.
/INTRA Pin
Rewriting of the second counter
CTFG Bit
Approx. 92
μ
s
(Increment of second counter)
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相關(guān)代理商/技術(shù)參數(shù) |
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| RV5C387A | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:I2C-bus Real-Time Clock ICs with Voltage Monitoring Function |
| RV5C387A_03 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC WITH VOLTAGE MONITORING FUNCTION |
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| RV5C387A-E2 | 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:I2C-bus Real-Time Clock ICs with Voltage Monitoring Function |
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