參數(shù)資料
型號： RV5C386A-E2
廠商： RICOH COMPANY LTD
元件分類： XO, clock
英文描述： I2C-bus Real-Time Clock ICs with Voltage Monitoring Function
中文描述： 0 TIMER(S), REAL TIME CLOCK, PDSO10
封裝： 4 X 2.90 MM, 1.20 MM HEIGHT, SSOP-10
文件頁數(shù)： 12/42頁
文件大?。?/td> 362K
代理商： RV5C386A-E2
RV5C386A PRELIMINARY
12345
- 12 -
13.2.2.
Control Register 2 (Address Fh)
D7
D6
D5
D4
D3
D2
CTFG
D1
WAFG
D0
DAFG
VDSL
VDET
SCRA-
TCH1
SCRA-
TCH1
0
XSTP SCRA-
TCH2
SCRA-
TCH2
0
(For Writing)
VDSL
VDET
XSTP
CTFG
WAFG
DAFG
(For Reading)
0
0
1
0
0
0
Default Settings *)
*) Default settings: Default value means read / written values when the XSTP bit is reset due to power-on from
0 volts or supply voltage drop.
(1) VDSL
Supply Voltage Monitoring Threshold Selection Bit
VDSL
0
Selecting the supply voltage monitoring threshold setting of 2.1v.
1
Selecting the supply voltage monitoring threshold setting of 1.6v.
The VDSL bit is intended to select the supply voltage monitoring threshold settings.
Description
(Default)
(2)
VDET
Supply Voltage Monitoring Result Indication Bit
VDET
0
Indicating supply voltage above the supply voltage monitoring
threshold settings.
1
Indicating supply voltage below the supply voltage monitoring
threshold settings.
Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will hold the
setting of 1. The VDET bit accepts only the writing of 0, which restarts the supply voltage monitoring circuit.
Conversely, setting the VDET bit to 1 causes no event.
(3) SCRATCH1
Scratch Bit 1
SCRATCH1
Description
0
1
The SCRATCH1 bit is intended for scratching and accepts the reading and writing of 0 and 1. The SCRATCH1
bit will be set to 0 when the XSTP bit is set to 1 in the Control Register 2.
(4) XSTP
Oscillation Halt Sensing Bit
XSTP
Description
0
Sensing a normal condition of oscillation
1
Sensing a halt of oscillation
The XSTP bit is for sensing a halt in the oscillation of the crystal oscillator.
*
The XSTP bit will be set to 1 once a halt in the oscillation of the crystal oscillator is caused by such events as
power-on from 0 volts and a drop in supply voltage. The XSTP bit will hold the setting of 1 even after the
restart of oscillation. As such, the XSTP bit can be applied to judge the validity of clock and calendar data
after power-on or a drop in supply voltage.
*
When the XSTP bit is set to 1, all bits will be reset to 0 in the Oscillation Adjustment Register, Control Register
1, and Control Register 2, stopping the output from /INTRA and /INTRB pins and starting the output of
32.768-kHz clock pulses from the 32KOUT pin.
*
The XSTP bit accepts only the writing of 0, which restarts the oscillation halt sensing circuit. Conversely,
setting the XSTP bit to 1 causes no event.
*
It is recommendable to frequently check the XSTP bit for setting errors or data garbles, which may seriously
affect the operation of the RV5C386A.
Description
(Default)
(Default)
(Default)
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