參數(shù)資料
型號(hào)： RV5C386A-E2
廠商： RICOH COMPANY LTD
元件分類： XO, clock
英文描述： I2C-bus Real-Time Clock ICs with Voltage Monitoring Function
中文描述： 0 TIMER(S), REAL TIME CLOCK, PDSO10
封裝： 4 X 2.90 MM, 1.20 MM HEIGHT, SSOP-10
文件頁(yè)數(shù)： 30/42頁(yè)
文件大?。?/td> 362K
代理商： RV5C386A-E2
RV5C386A PRELIMINARY
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Notes:
1) Oscillation adjustment does not affect the frequency of 32.768-kHz clock pulses output from the 32KOUT pin.
2) Oscillation adjustment value range: When the oscillation frequency is higher than the target frequency
(causing a time count gain), an appropriate time count gain ranges from -3.05ppm to -189.2ppm with the
settings of "0, 0, 0, 0, 0, 1, 0" to "0, 1, 1, 1, 1, 1, 1" written to the F6, F5, F4, F3, F2, F1, and F0 bits in the
oscillation adjustment register, thus allowing correction of a time count gain of up to +189.2ppm. Conversely,
when the oscillation frequency is lower than the target frequency (causing a time count loss), an appropriate
time count gain ranges from +3.05ppm to +189.2ppm with the settings of "1, 1, 1, 1, 1, 1, 1" to "1, 0, 0, 0, 0, 1,
0" written to the F6, F5, F4, F3, F2, F1, and F0 bits in the oscillation adjustment register, thus allowing
correction of a time count loss of up to -189.2ppm.
Oscillation Halt Sensing and Supply Voltage Monitoring
The oscillation halt sensing circuit is configured to record a halt on oscillation by 32.768-kHz clock pulses.
The supply voltage monitoring circuit is configured to record a drop in supply voltage below a threshold
voltage of 2.1 or 1.6v. Both the flag bits of these circuits (i.e. the XSTP bit for the former and the VDET bit
for the latter) in the control register 2, are maintained “1” until they are reset by the setting of 0 in the same
bits.
When the XSTP bit is set to 1 for the oscillation halt sensing circuit, the VDET bit is reset to 0 for the supply
voltage monitoring circuit. The relationship between the XSTP and VDET bits is shown in the table below.
14.3.
XSTP
0
0
1
VDET
0
1
*
Conditions of supply voltage and oscillation
No drop in supply voltage below threshold voltage and no halt in oscillation
Drop in supply voltage below threshold voltage and no halt in oscillation
Halt on oscillation
32768Hz Oscillation
Supply voltage monitoring
(VDET)
Oscillation halt sensing
(XSTP)
Threshold voltage (2.1V or 1.6V)
Normal voltage detector
VDET
←
0
Supply voltage
XSTP,VDET
←
0
Internal initiali-
zation period
(1 to 2 sec.)
XSTP,VDET
←
0
When the XSTP bit is set to 1 in the control register 2, the F6 to F0, WALE, DALE, /12
24, SCRATCH3, TEST,
CT2, CT1, CT0, VDSL, VDET, SCRATCH1, SCRATCH2, CTFG, WAFG, and DAFG bits are reset to 0 in the
oscillation adjustment register, the control register 1, and the control register 2. The XSTP bit is also set to 1
at power-on from 0 volts. Note that the XSTP bit may be locked upon instantaneous power-down.
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