參數(shù)資料
型號: RS5C313
廠商: RICOH COMPANY LTD
元件分類: XO, clock
英文描述: PrimeSTACK up to 1700V Half Bridge
中文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO8
封裝: 0.65 MM PITCH, SSOP-8
文件頁數(shù): 21/32頁
文件大?。?/td> 267K
代理商: RS5C313
Considerations in Use of XSTP Bit
Ensure error-free oscillation halt sensing by preventing the following:
1) Instantaneous disconnection of V
DD
2) Condensation on the crystal oscillator
3) Generation of noise on the PCB in the crystal oscillator
4) Application of voltage exceeding prescribed maximum ratings to the indi-
vidual pins of the IC
RS5C313
18
Oscillation Halt can be sensed by setting the XSTP (oscillator halt sensing) bit to 0 (after writing data to the control
register) and then monitoring the XSTP bit. Upon oscillator halt sensing, the XSTP bit is switched from 0 to 1. This
function can be applied to judge clock data validity.
5. Oscillator Halt Sensing
Writing of data to
control register
(in the presence of oscillation)
Power-on
from 0V
*
1
Oscillation restart
*
2
Oscillation halt
XSTP
*
1) While the CE pin is held at the low level the XSTP bit is set to 1 upon power-on from 0 V. Note that any instantaneous power disconnection may
cause operational failure. When the CE pin is held at the high level oscillation halt is not sensed and the value of the XSTP bit when the CE pin is
held at the low level is retained.
*
2) Once oscillation halt has been sensed, the XSTP bit is held at 1 even if oscillation is restarted.
6. Typical Power Supply Circuit
OSCIN
OSCOUT
VDD
VSS
RS5C313
B
A
System supply voltage
INTR
1) Connect the capacitance of the oscillation circuit to the VSS pin.
2) Mount the high- and low-frequency by-pass capacitors in parallel
and very close to the RS5C313.
3) Connect the pull-up resistor of the INTR pin to two different posi-
tions depending on whether the resistor is in use during battery
back-up.
When not in use during battery back-up
- - - - - Position A in the left figure
When in use during battery back-up
- - - - - Position B in the left figure
4) Timing of power supply on / off and CE terminal refer to lower part
plan.
C
0V
V
DD
CE
D
0.2V
DD
MIN. 0μs
MIN. 0μs
MIN. 0μs
C,D,E : The lower limit voltage for CPU operation
0.2V
DD
0.2V
DD
Battery voltage
System supply
voltage
E
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