參數(shù)資料
型號(hào): RS5C313
廠商: RICOH COMPANY LTD
元件分類: XO, clock
英文描述: PrimeSTACK up to 1700V Half Bridge
中文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO8
封裝: 0.65 MM PITCH, SSOP-8
文件頁(yè)數(shù): 19/32頁(yè)
文件大?。?/td> 267K
代理商: RS5C313
Considerations
When the power turns on from 0V, the CE pin should be set low or open once.
RS5C313
16
1) Switching the CE pin to the high level enables both the SCLK and SIO pins, allowing data to be serially read from and
written to the SIO pin in synchronization with shift clock pulses input from the SCLK pin.
2) Switching the CE pin to the low level or opening it disables both the SCLK and SIO pins, causing high impedance and
resetting the internal interfacing circuits such as the shift register.
3) The CE pin should be held at the low level or open state when no access is made to the RS5C313. The CE pin incorpo-
rates a pull-down resistor.
4) During system power-down (being back-up battery powered), the low-level input of the CE pin should be brought as close
as possible to the VSS level to minimize the loss of charge in the battery.
5) Holding the CE pin at the high level for more than 2.5 seconds mainly forces 1Hz interrupt pulses to be output from the
INTR pin for oscillation frequency measurement. When the CE pin is held at the high level for less than 1.5 seconds, no
pulse is output.
6) The CE pin should be held at the low level in order to enable oscillator halt sensing. Holding the CE pin at the high level,
therefore, disables oscillator halt sensing, retaining the value of the XSTP (oscillator halt sensing) bit which exists imme-
diately before the CE pin is switched to the high level.
3. CE Pin
SCLK
SIO
CE
Shift clock pulses
Address & Write data
Read data
Reading control bits
Control bits
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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