參數(shù)資料
型號(hào)： RS5C313
廠商： RICOH COMPANY LTD
元件分類： XO, clock
英文描述： PrimeSTACK up to 1700V Half Bridge
中文描述： 0 TIMER(S), REAL TIME CLOCK, PDSO8
封裝： 0.65 MM PITCH, SSOP-8
文件頁(yè)數(shù)： 12/32頁(yè)
文件大?。?/td> 267K
代理商： RS5C313
Note
RS5C313
9
2.1-2 (BSY)
When the BSY bit is 1, the clock and calendar counters are being updated. Consequently, write operation should be performed
for the counters when the BSY bit is 0. Meanwhile, read operation is normally performed for the counters when the BSY bit is 0,
but can be performed without checking the BSY bit as long as appropriate software is provided for preventing read errors(Refer
to the item 11.3 Read Operation from Clock and Calendar Counters). The BSY bit is set to 1 in the following three cases:
MAX. 122.1μs
Setting of the ADJ bit to 1
Completion of second digit adjustment
(1) Adjustment of second digits by
±30 seconds
(2) Second digit increment by 1
(Subject to 1-second digit carry
when the WTEN bit is switched
from 0 to 1)
(3) Ordinary 1-second digit carry
MAX.91.6μs
Setting of the WTEN bit to 1
End of second digit increment by 1
91.6μs
End of second digit carry pulse
2.1-3 (WTEN)
The WTEN bit should be set to 0 to check that the BSY bit is 0 when performing read and write operations for the clock and
calendar counters. For read operation, the WTEN bit may be left as 1 without checking the BSY bit as long as appropriate
measures such as read repetition are provided for preventing read errors(Refer to the item 11.3 Read Operation from Clock
and Calendar Counters). The WTEN bit should be set to 1 after completing read and write operations, or will automatically
be set to 1 by switching the CE pin to the low level. If 1-second digit carry occurs when the WTEN bit is 0, a second digit
increment by 1 occurs when the WTEN bit is set to 1.
2.1-4 (XSTP)
The XSTP bit senses the ocilllator halt. When the CE pin is held at the low level, the XSTP bit is set to 1 once the crystal
oscillator is stopped after initial power-on or supply voltage drop and left to be 1 after it is restarted. When the CE pin is held
at the high level, the XSTP bit is left as it was when the CE pin was held at the low level without checking oscillation stop. As
such, the XSTP bit can be used to validate clock and calendar count data after power-on or supply voltage drop. The XSTP bit
is set to 0 when write operation is performed for the control register (at Eh) (during normal oscillation).
2.1-5 (12/24)
The 12/24 bit specifies time digit display in BCD code.
00
01
02
03
04
05
06
07
08
09
10
11
12(AM12)
01(AM 1)
02(AM 2)
03(AM 3)
04(AM 4)
05(AM 5)
06(AM 6)
07(AM 7)
08(AM 8)
09(AM 9)
10(AM10)
11(AM11)
12
13
14
15
16
17
18
19
20
21
22
23
32(PM12)
21(PM 1)
22(PM 2)
23(PM 3)
24(PM 4)
25(PM 5)
26(PM 6)
27(PM 7)
28(PM 8)
29(PM 9)
30(PM10)
31(PM11)
24-hour time display system 12-hour time display system 24-hour time display system 12-hour time display system
Either the 12-hour or 24-hour time display system should be selected before time setting (e.g. during initialization after power-on).
If the WTEN bit is 0 for 1/1024 second and more, second digit increment by 1 may not occur. (Refer to the item 11.3
Read Operation from Clock and Calendar Counters).
相關(guān)PDF資料
PDF描述
RS5C314 PrimeSTACK up to 1700V Half Bridge
RS5C316 MINIATURE POWER RELAY
RS5C316A ULTRA-COMPACT SERIAL ALARM REAL-TIME CLOCK ICs
RS5C316B ULTRA-COMPACT SERIAL ALARM REAL-TIME CLOCK ICs
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
RS5C314 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:ULTRA-COMPACT REAL-TIME CLOCK IC
RS5C316 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:ULTRA-COMPACT SERIAL ALARM REAL-TIME CLOCK ICs
RS5C316A 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:ULTRA-COMPACT SERIAL ALARM REAL-TIME CLOCK ICs
RS5C316A/B 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:real-time clock ICs
RS5C316B 制造商:RICOH 制造商全稱:RICOH electronics devices division 功能描述:ULTRA-COMPACT SERIAL ALARM REAL-TIME CLOCK ICs
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