參數(shù)資料
型號(hào): RD28F3204W30T85
廠商: INTEL CORP
元件分類(lèi): 存儲(chǔ)器
英文描述: 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O and SRAM (W30)
中文描述: SPECIALTY MEMORY CIRCUIT, PBGA80
封裝: 14 X 8 MM, 0.80 MM PITCH, STACK, CSP-80
文件頁(yè)數(shù): 46/82頁(yè)
文件大小: 749K
代理商: RD28F3204W30T85
28F6408W30, 28F3204W30, 28F320W30, 28F640W30
40
Preliminary
12.0
Flash AC Characteristics
12.1
Flash Read Operations
#
Sym
Parameter
(1,2)
Speed
70
85
Unit
Note
Min
Max
Min
Max
R1
t
AVAV
Read Cycle Time
3
70
85
ns
R2
t
AVQV
Address to Output Delay
3
70
85
ns
R3
t
ELQV
CE# Low to Output Delay
70
85
ns
R4
t
GLQV
OE# Low to Output Delay
5
30
30
ns
R5
t
PHQV
RST# High to Output Delay
150
150
ns
R7
t
GLQX
OE# Low to Output in Low-Z
5, 6
0
0
ns
R8
t
EHQZ
CE# High to Output in High-Z
6
25
25
ns
R9
t
GHQZ
OE# High to Output in High-Z
5, 6
25
25
ns
R10
t
OH
CE#, (OE#) High to Output in Low-Z
5, 6
0
0
ns
R101
t
AVVH
Address Setup to ADV# High
10
10
ns
R102
t
ELVH
CE# Low to ADV# High
10
10
ns
R103
t
VLQV
ADV# Low to Output Delay
70
85
ns
R104
t
VLVH
ADV# Pulse Width Low
10
10
ns
R105
t
VHVL
ADV# Pulse Width High
6
10
10
ns
R106
t
VHAX
Address Hold from ADV# High
4
9
9
ns
R108
t
APA
Page Address Access Time
4
25
25
ns
R200
f
CLK
CLK Frequency
40
33
MHz
R201
t
CLK
CLK Period
25
30
ns
R202
t
CH/L
CLK High or Low Time
9.5
9.5
ns
R203
t
CHCL
CLK Fall or Rise Time
3
5
ns
R301
t
AVCH
Address Valid Setup to CLK
9
9
ns
R302
t
VLCH
ADV# Low Setup to CLK
10
10
ns
R303
t
ELCH
CE# Low Setup to CLK
9
9
ns
R304
t
CHQV
CLK to Output Delay
20
22
ns
R305
t
CHQX
Output Hold from CLK
5
5
ns
R306
t
CHAX
Address Hold from CLK
4
10
10
ns
R307
t
CHTL/
H
CLK to WAIT Asserted
20
22
ns
R308
t
ELTL
OE# Low to WAIT Active
7
20
22
ns
R309
t
EHTZ
CE# (OE#) High to WAIT High-Z
6, 7
25
25
ns
R310
t
EHEL
CE# Pulse Width High
7
20
20
ns
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