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型號：	RC7100
文件頁數(shù)：	877/1328頁
文件大?。?/td>	9519K
代理商：	RC7100

PRODUCT SPECIFICATION

Functional Description

The RC6100 block diagram is shown in Figure 1. Baseband

composite video may be applied to either the FILTIN or

CVIN input, depending upon whether the lowpass filter cir-

cuit function is desired. Use of the lowpass filter is desirable

whenever the input video signal contains impulse noise or

glitches that can cause jitter on the sync and clock output sig-

nals. Signals that require lowpass filtering should be input at

FILTIN and the lowpass filter output (FILTOUT) should be

connected to the CVIN input. However, video signals that do

not require noise filtering should be input directly at CVIN to

optimize performance. The FILTIN and CVIN inputs can

also receive composite sync or horizontal sync signals at

CMOS or TTL levels.

The input VSYNC is intended for those applications in

which the horizontal and vertical sync signals have already

been separated. In this mode, horizontal sync should be

applied to CVIN and vertical sync applied to VSYNC. These

two signals will be combined to form CSYNC and used by

the timing generator to form HRESET, VRESET, and the

other timing control signals. The VSYNC input is active low

and is held at logic high via an internal bias network. If

VSYNC is left open, there is no effect on signal processing.

The sync separator extracts a composite sync signal from the

composite video, or creates composite sync from separate

horizontal and vertical sync inputs. This signal is available at

the CSYNC output. Composite sync is also used to control

the timing generator, which is the workhorse function of the

The timing generator contains programmable dividers for

generating and controlling the pixel clock. The selection of

pixel clock frequencies is controlled via logic inputs NTSC/

PAL, S0, and S1. Table 1 shows the states of these inputs and

the corresponding clock frequencies. The timing generator

also provides the following output signals: CLAMP, VRE-

SET, FIELDID, HRESET, FHOUT, and CLKDIV2. The

CLAMP output is an active-low rectangular pulse

s duration, the origination of which is timed by the rising-

edge of CSYNC; the pulse is active during the horizontal

back-porch interval, as shown in Figure 2. The CLAMP out-

put is also active during the vertical blanking interval. The

VRESET output is a short vertical sync signal that is logic

low for the duration of the scan line that follows the first ser-

ration pulse of the vertical interval, as shown in Figure 3.

HRESET is a horizontal sync signal that is set to logic low

for one period of the pixel clock (CLKOUT); it is also phase

coherent with the pixel clock. FHOUT is a clock signal at the

horizontal frequency. It is normally connected to FHIN and

used as the VCO (feedback) input to the loop phase compar-

ator. The timing of HRESET relative to FHOUT is shown in

Figure 4. (Note: the drawing exaggerates delays t1 and t2.)

The FIELDID output goes to logic low immediately after the

Block Diagram

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