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RC7106
PRODUCT SPECIFICATION
8
Writing Data Bytes
Each bit of the 10 data bytes controls a particular device
function except for the “reserved bits”. These must be pre-
served by writing a logic 0. Bit 7, the MSB, is written first.
See Table 4 for bit descriptions of Data Bytes 1-4.
Table 5 shows additional frequency selections that are pro-
grammable via the serial data interface.
Table 7 shows the mode select functions for Byte 3, bits 1
and 0.
Table 4. Data Bytes 1-4 Serial Configuration Map
Bit(s)
Data Byte 1
7
6
5
4
3
2
1
0
Data Byte 2
7
6
5
4
3
2
1
0
Data Byte 3
7
6
5
4
3
2
1
0
Data Byte 4
7
6
5
4
3
2
1
0
Affected Pin
Pin No.
Control Function
Bit Control
Default
Pin Name
0
1
40
38
37
42
47
46
2
3
CPU0
CPU1
CPU2
CPU/2
IOAPIC0
IOAPIC1
REF0
REF1
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
18
17
15
14
12
11
9
8
PCI7
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
PCI_F
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
34
33
32
-
-
-
-
-
3V66_0
3V66_1
3V66_2
-
-
-
-
-
Clock Output Disable
Clock Output Disable
Clock Output Disable
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Disable
Disable
Disable
-
-
-
-
-
Enable
Enable
Enable
-
-
-
-
-
1
1
1
0
0
0
0
0
26
27
-
22
21
20
-
-
24_48MHz
48MHz
-
PCI10
PCI9
PCI8
-
-
Clock Output Disable
Clock Output Disable
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
(Reserved)
(Reserved)
Disable
Disable
-
Disable
Disable
Disable
-
-
Enable
Enable
-
Enable
Enable
Enable
-
-
1
1
0
1
1
1
0
0