參數(shù)資料
型號: PXA270
廠商: Intel Corp.
英文描述: Electrical, Mechanical, and Thermal Specification
中文描述: 電氣,機械和熱規(guī)格
文件頁數(shù): 97/126頁
文件大小: 1563K
代理商: PXA270
Electrical, Mechanical, and Thermal Specification
6-33
Intel PXA270 Processor
AC Timing Specifications
6.4.5
SRAM Parameters and Timing Diagrams
The following sections describe the read/write parameters and timing diagrams for SRAM
interfaces with the memory controller.
6.4.5.1
SRAM Read Parameters and Timing Diagrams
The timing for a read access is identical to that for a non-burst ROM read (see
Figure 6-11
). The
timings listed in
Table 6-16
for ROM reads are also used for SRAM reads. See
Figure 6-11
and
Figure 6-14
for timings diagrams representing 16-bit SRAM transferring four, two, and one byte(s)
during read-bus tenures.
6.4.5.2
SRAM Write Parameters and Timing Diagrams
Figure 6-22
and
Figure 6-23
show the timing for 32-bit and 16-bit SRAM writes.
Table 6-19
lists
the timings used in
Figure 6-22
and
Figure 6-23
.
Figure 6-21. 16-Bit Flash Write Timing
addr
0b0
Bytes 1:0
0b00
tflashCD
tflashDSWH
tflashWL
tflashDH
tflashCEH
tflashCES
tflashAS
Applies to:
16-bit Non-Burst Flash
16-bit Burst Flash
NOTE: MSC1[RDN2] = 2, MSC1[RDF2] = 1, MSC1[RRR2] = 2
CLK_MEM
nCS<2>
MA<25:1>
MA<0>
nWE
nOE
RDnWR
MD<15:0>
DQM<1:0>
nADV(nSDCAS)
nCSx or nSDCSx
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