參數(shù)資料
型號(hào)： PXA270
廠商： Intel Corp.
英文描述： Electrical, Mechanical, and Thermal Specification
中文描述： 電氣，機(jī)械和熱規(guī)格
文件頁(yè)數(shù)： 93/126頁(yè)
文件大?。?/td> 1563K
代理商： PXA270
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Electrical, Mechanical, and Thermal Specification
6-29
Intel PXA270 Processor
AC Timing Specifications
The burst read example shown in
Figure 6-18
represents waveforms that result when
SXCNFG[SXCLx] is configured as 0b0100, representing a frequency configuration code equal to
3. The following example can be used to help determine the appropriate setting for
SXCNFG[SXCLx].
Parameters defined by the processor:
tffSDOH (max) = SDCLK<0> to CE# (nCE), ADV# (nADV), or address valid, whichever
occurs last
tffSDIS (min) = Data setup to SDCLK<0>
Parameters defined by flash memory:
tVLQV (min) = ADV# low to output delay
tVLCH (min) = ADV# low to clock
tCHQV (max) = SDCLK<0> to output valid
Use the following equations when calculating the frequency configuration code:
(1) SDCLK period = (1 / frequency)
(2) n (SDCLK period)
tVLQV - tVLCH - tCHQV
(3) n = (tVLQV - tVLCH - tCHQV) / SDCLK period, where
n = frequency configuration code rounded up to integer value
(4) SDCLK period
tCHQV + tffSDIS
Example
The timing information below is only an example. See
Table 6-17
for actual synchronous AC
timings.
SDCLK<0> frequency = 50 MHz
tVLQV = 70 ns (typical timing from synchronous flash memory)
tVLCH = 10 ns (min)
tCHQV = 14 ns (min)
From Eq.(1):
1 / 50 (MHz) = 20 ns
From Eq.(2):
n(20 ns)
≥
46 ns
n = (46 / 20) ns = 2.3 ns
n = 3
n(20 ns)
≥
70 ns - 10 ns - 14 ns
Use equation 4 to help verify the maximum possible frequency at which the synchronous flash
memory can run with the memory controller. The following example uses equation 4:
SDCLK<0> frequency = 66 MHz
tCHQV = 11 ns (max)
tffSDIS = 3 ns (min)
From Eq. (1):
From Eq. (4):
1 / 66 (MHz) = 15.15 ns
15.15 ns
≥
11 ns + 3 ns
15.15 ns
≥
14 ns
The results from this example indicate that the 66-MHz memory works without problems with the
memory controller.
Note:
All AC timings must be considered to avoid timing violations in the memory-to-memory-controller
interface.
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