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參數(shù)資料
| 型號： | PXA270 |
| 廠商： | Intel Corp. |
| 英文描述： | Electrical, Mechanical, and Thermal Specification |
| 中文描述： | 電氣，機械和熱規(guī)格 |
| 文件頁數(shù)： | 73/126頁 |
| 文件大?。?/td> | 1563K |
| 代理商： | PXA270 |
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Electrical, Mechanical, and Thermal Specification
6-9
Intel PXA270 Processor
AC Timing Specifications
6.2.6.1
GPIO states in Deep-Sleep mode
If the external high voltage power domains (VCC_IO, VCC_MEM, VCC_BB, VCC_LCD,
VCC_USB, VCC_USIM) remain powered on during deep-sleep, the PGSR values are driven onto
all the GPIO pins (that are configured as outputs) for a finite time period, then the pins default to
the reset state (Pu/Pd) as described in Chapter 2 of this manual. This sequence occurs for either
software initiated or fault initiated deep-sleep entry.
Note:
GPIOs<0,1,3,4,9,10> never float. They are powered from VCC_BATT so when the system and the
core power domains are removed (controlled by SYS_EN and PWR_EN), the Pu/Pd resistors are
still enabled due to VCC_BATT remaining on.
The delay between the initiation of deep-sleep mode and enabling the GPIO Pu/Pd states, is system
dependant because the processor is performing an unpredictable workload and requires an
unknown amount of time to complete current processes. Refer to the deep-sleep mode, “Clocks and
Power” section of the
Intel PXA27x Processor Family Developers Manual
for a description on
deep-sleep mode entry sequence.
Table 6-8
shows the time period that the GPIO pull-up/pull-downs are enabled. Listed below are
the regulators and converter naming conventions:
L1 = Sleep/Deep-Sleep Linear Regulator
L2 = High-Current Linear Regulator
DC2DC = Sleep/Deep-Sleep DC-DC Converter
Note:
If the
external high voltage power domains
(VCC_IO, VCC_MEM, VCC_BB, VCC_LCD,
VCC_USB, VCC_USIM) are powered off during deep-sleep mode, the GPIOs behave the same as
described above; however, they float after the supplies are removed.
Table 6-8. GPIO Pu/Pd Timing Specifications for Deep-Sleep Mode
Description
L2
L1
DC2DC
Units
Duration of the GPIO Pu/Pd states being
enabled and the de-assertion of
PWR_EN
0.1
0.13
1.13
msec
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