參數(shù)資料
型號(hào)： PXA270
廠商： Intel Corp.
英文描述： Electrical, Mechanical, and Thermal Specification
中文描述： 電氣，機(jī)械和熱規(guī)格
文件頁數(shù)： 67/126頁
文件大?。?/td> 1563K
代理商： PXA270
Electrical, Mechanical, and Thermal Specification
6-3
Intel PXA270 Processor
AC Timing Specifications
5. The processor asserts the PWR_EN signal to enable the power supplies VCC_CORE,
VCC_SRAM, and VCC_PLL. These supplies can turn on in any order but must all be
established within 125 milliseconds of the assertion of PWR_EN.
6. The external power-control subsystem de-asserts nVDD_FAULT to signal that all system
power supplies have been properly established.
7. The processor de-asserts nRESET_OUT and enters run mode, executing code from the reset
vector.
Note:
nBATT_FAULT must be high before nRESET is de-asserted. Otherwise, the processor will not
begin the power-on sequencing event. nVDD_FAULT is sampled only when the SYS_DEL and
PWR_DEL timers have expired. Refer to the
Intel PXA27x Processor Family Developer’s
Manual
, “Initial Power On” and “Deep-Sleep Exit States” for a state diagram.
Figure 6-2. Power On Reset Timing
Table 6-2. Power-On Timing Specifications (Sheet 1 of 2)(OSCC[CRI] = 0)
Symbol
Description
Min
Typical
Max
Units
t
1
Delay from VCC_BATT assertion to
nRESET de-assertion
10
—
—
ms
t
2
Delay from nRESET de-assertion to
SYS_EN assertion
—
10
1
—
ms
t
3
Delay from SYS_EN assertion to
PWR_EN assertion
—
125
—
ms
t
4
Power supply stabilization time (time to
the deassertion of nVDD_FAULT after the
assertion of PWR_EN)
—
—
120
ms
t
5
Delay from the assertion of PWR_EN to
the de-assertion of nRESET_OUT
—
125
—
ms
t
bramp
VCC_BATT power-on Ramp Rate
—
10
12
mV/uS
VCC_USB, VCC_IO, VCC_MEM,
VCC_BB, VCC_LCD, VCC_USIM
PWR_EN
VCC_CORE, VCC_SRAM,
VCC_PLL
nBATT_FAULT
nRESET
SYS_EN
nVDD_FAULT
VCC_BATT
nRESET_OUT
t
1
t
3
t
5
t
2
t
4
t
sysramp
t
bramp
t
pwrramp
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