參數(shù)資料
型號： PXA270
廠商： Intel Corp.
英文描述： Electrical, Mechanical, and Thermal Specification
中文描述： 電氣，機械和熱規(guī)格
文件頁數(shù)： 68/126頁
文件大?。?/td> 1563K
代理商： PXA270
6-4
Electrical, Mechanical, and Thermal Specification
Intel PXA270 Processor
AC Timing Specifications
6.2.2
Hardware Reset Timing
The timing sequences shown in
Figure 6-3
for hardware reset and the specifications in
Table 6-3
and
Table 6-4
assume stable power supplies at the assertion of nRESET. Follow the timings
indicated in
Section 6.2.1
if the power supplies are unstable.
t
sysramp
Power-on Ramp Rate for all external high
-voltage power domains
—
10
12
mV/uS
t
pwrramp
Power-on Ramp Rate for all external low
-voltage power domains (including
dynamic voltage changes on
VCC_CORE)
—
10
12
mV/uS
NOTES:
1. If the OSCC[CRI] =1 then the delay from nRESET de-assertion to SYS_EN assertion is 3000mS
NOTE:
This long delay is attributed to the fact that when the CRI bit is read as 1, (which indicates that the
CLK_REQ pin was floated during a hardware or power-on reset) the processor oscillator is supplied
externally. This then forces the system to wait for the 32 kHz oscillator and the 13 MHz oscillator to
stabilize.
Table 6-2. Power-On Timing Specifications (Sheet 2 of 2)(OSCC[CRI] = 0)
Symbol
Description
Min
Typical
Max
Units
Figure 6-3. Hardware Reset Timing
Table 6-3. Hardware Reset Timing Specifications (OSCC[CRI] = 0)
Symbol
Description
Min
Typical
Max
Units
t
6
Delay between nRESET asserted and
nRESET_OUT asserted
—
< 100 ns
10
ms
t
7
Assertion time of nRESET
6
—
—
ms
t
8
Delay between nRESET de-asserted and
nRESET_OUT de-asserted
256
—
265
ms
nRESET
nRESET_OUT
t7
NOTE: nBATT_FAULT and nVDD_FAULT must be deasserted during the reset sequence.
t6
t8
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