參數(shù)資料
型號: PSD913F2V
英文描述: 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA7260 with Standard Packaging
中文描述: 可配置的存儲系統(tǒng)級芯片的8位微控制器
文件頁數(shù): 33/94頁
文件大?。?/td> 463K
代理商: PSD913F2V
PSD913F1
Preliminary
32
RESET
D0 - D7
R/W
D0
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D1
D2
D3
D4
D5
D6
D7
PAGE
REGISTER
PGR0
PGR1
PGR2
PGR3
DPLD
AND
GPLD
INTERNAL
SELECTS
AND LOGIC
FLASH
PLD
PGR4
PGR5
PGR6
PGR7
Figure 10. Page Register
The
PSD913F1
Functional
Blocks
(cont.)
9.1.4 Page Register
The eight bit Page Register increases the addressing capability of the microcontroller by a
factor of up to 256. The contents of the register can also be read by the microcontroller. The
outputs of the Page Register (PGR0-PGR7) are inputs to the PLD and can be included in
the Flash Memory, EEPROM, and SRAM chip select equations.
If memory paging is not needed, or if not all 8 page register bits are needed for memory
paging, then these bits may be used in the PLD for general logic. See Application
Note.
Figure 10 shows the Page Register. The eight flip flops in the register are connected to the
internal data bus D0-D7. The microcontroller can write to or read from the Page Register.
The Page Register can be accessed at address location CSIOP + E0h.
相關(guān)PDF資料
PDF描述
PSD913F2(中文) Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng))
PSD934F2(中文) Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng))
PSD913F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng))
PSD934F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng))
PSD935G2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(8位微控制器片上存儲器可編程外設(shè))
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