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| 型號： | PSD913F2V |
| 英文描述： | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA7260 with Standard Packaging |
| 中文描述： | 可配置的存儲系統(tǒng)級芯片的8位微控制器 |
| 文件頁數(shù)： | 14/94頁 |
| 文件大小： | 463K |
| 代理商： | PSD913F2V |
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Preliminary
PSD913F1
13
Table 5.
PSD913F1
Pin
Descriptions
(cont.)
Pin Name
Pin*
(PLCC)
Type
Description
PC7
11
I/O
PC7 pin of Port C. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. Input to the PLDs.
3. DBE — active-low Data Byte Enable input from 68HC912
type MCUs.
This pin can be configured as a CMOS or Open Drain output.
PD0
10
I/O
PD0 pin of Port D. This port pin can be configured to have
the following functions:
1. ALE/AS input latches address output from the MCU.
2. MCU I/O — write or read from a standard output or input
port.
3. Input to the PLDs.
4. General purpose PLD output.
PD1
9
I/O
PD1 pin of Port D. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. Input to the PLDs.
3. General purpose PLD output.
4. CLKIN — clock input to the automatic power-down unit’s
power-down counter, and the PLD AND array.
PD2
8
I/O
PD2 pin of Port D. This port pin can be configured to have
the following functions:
1. MCU I/O — write to or read from a standard output or
input port.
2. Input to the PLDs.
3. General purpose PLD output.
4. CSI — chip select input. When low, the MCU can access
the PSD memory and I/O. When high, the PSD memory
blocks are disabled to conserve power.
Power pins
V
CC
GND
15, 38
1,16,26
Ground pins
Port A
Port B
Microcontroller
8051XA (8-bit)
80C251 (page mode)
All other 8-bit
multiplexed
8-bit non-multiplexed
bus
Port A (3:0)
N/A
N/A
Port A (7:4)
Address [7:4]
N/A
Port B (3:0)
Address [11:8]
Address [11:8]
Port B (7:4)
N/A
Address [15:12]
Address [3:0]
Address [7:4]
Address [3:0]
Address [7:4]
N/A
N/A
Address [3:0]
Address [7:4]
Table 6. I/OPort Latched Address Output Assignments*
N/A = Not Applicable
*
*
Refer to the I/O Port Section on how to enable the Latched Address Output function.
*
*
The pin numbers in this table are for the PLCC package only. See the package information section for pin
numbers on other package types.
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PDF描述 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PSD913F2V-12B81 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F2V-12B81I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F2V-12J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F2V-12J1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 3.3 V |
| PSD913F2V-12JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
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