- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368267 > PSD913F2V 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA7260 with Standard Packaging PDF資料下載
參數(shù)資料
| 型號： | PSD913F2V |
| 英文描述： | 200V 100kRad Hi-Rel Single N-Channel TID Hardened MOSFET in a SMD-2 package; A IRHNA7260 with Standard Packaging |
| 中文描述： | 可配置的存儲系統(tǒng)級芯片的8位微控制器 |
| 文件頁數(shù)： | 15/94頁 |
| 文件大?。?/td> | 463K |
| 代理商： | PSD913F2V |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁
PSD913F1
Preliminary
14
Table 7 shows the offset addresses to the PSD913F1 registers relative to the CSIOP base
address. The CSIOP space is the 256 bytes of address that is allocated by the user to the
internal PSD913F1 registers. Table 7 provides brief descriptions of the registers in CSIOP
space. For a more detailed description, refer to section 9.
Table 7. Register Address Offset
8.0
PSD913F1
Register
Description
and Address
Offset
Register Name
Port A Port B Port C Port D Other*
Description
Data In
00
01
10
11
Reads Port pin as input,
MCU I/O input mode
Control
02
03
Selects mode between
MCU I/O or Address Out
Stores data for output
to Port pins, MCU I/O
output mode
Data Out
04
05
12
13
Direction
06
07
14
15
Configures Port pin as
input or output
Configures Port pins as
either CMOS or Open
Drain on some pins, while
selecting high slew rate
on other pins.
Drive Select
08
09
16
17
Flash Protection
C0
Read only – Flash Sector
Protection
PSD/EE
Protection
Read only – PSD Security
and EEPROM Sector
Protection
C2
PMMR0
B0
Power Management
Register 0
PMMR2
B4
Power Management
Register 2
Page
E0
Page Register
Places PSD memory
areas in Program and/or
Data space on an
individual basis.
VM
E2
*
Other registers that are not part of the I/O ports.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD913F2(中文) | Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng)) |
| PSD934F2(中文) | Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng)) |
| PSD913F2 | Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng)) |
| PSD934F2 | Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng)) |
| PSD935G2 | Configurable Memory System on a Chip for 8-Bit Microcontrollers(8位微控制器片上存儲器可編程外設(shè)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD913F2V-12B81 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F2V-12B81I | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F2V-12J | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
| PSD913F2V-12J1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 3.3 V |
| PSD913F2V-12JI | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。