參數(shù)資料
型號(hào): PSD813F
廠商: 意法半導(dǎo)體
英文描述: Flash In-System-Programmable Microcontroller Peripherals(閃速,在系統(tǒng)可編程微控制器外圍器件,1M位閃速存儲(chǔ)器,256K位EEPROM,16K位SRAM)
中文描述: Flash在系統(tǒng)可編程微控制器外圍設(shè)備(閃速,在系統(tǒng)可編程微控制器外圍器件,100萬(wàn)位閃速存儲(chǔ)器,256K位的EEPROM,16K的位的SRAM)
文件頁(yè)數(shù): 54/130頁(yè)
文件大小: 650K
代理商: PSD813F
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PSD813F Famly
Prelimnary
50
The
PSD813F
Functional
Blocks
(cont.)
9.3.4 Data Byte Enable Reference
Microcontrollers have different data byte orientations. The following table shows how the
PSD813F interprets byte/word operations in different bus write configurations. Even-byte
refers to locations with address A0 equal to zero and odd byte as locations with A0 equal
to one.
BHE
A0
D7-D0
X
X
0
1
Even Byte
Odd Byte
Table 18. Eight-Bit Data Bus
9.3.5 Microcontroller Interface Examples
Figures 20 through 24 show examples of the basic connections between the PSD813F
and some popular microcontrollers. The PSD813F Control input pins are labeled as to the
microcontroller function for which they are configured. The MCU interface is specified using
the PSDsoft Configuration.
9.3.5.1 80C31
Figure 20 shows the interface to the 80C31, which has an 8-bit multiplexed address/data
bus. The lower address byte is multiplexed with the data bus. The microcontroller control
signals PSEN, RD, and WR may be used for accessing the internal memory components
and I/O Ports. The ALE input (pin PD0) latches the address.
9.3.5.2 80C251
The Intel 80C251 microcontroller features a user-configurable bus interface with four
possible bus configurations, as shown in Table 19.
Configuration 1 is 80C31 compatible, and the bus interface to the PSD813F is identical to
that shown in Figure 20. Configurations 2 and 3 have the same bus connection as shown in
Figure 21. There is only one read input (PSEN) connected to the Cntl1 pin on the
PSD813F. The A16 connection to the PA0 pin allows for a larger address input to the
PSD813F. Configuration 4 is shown in Figure 22. The RD signal is connected to Cntl1 and
the PSEN signal is connected to the CNTL2.
The 80C251 has two major operating modes: Page Mode and Non-Page Mode. In
Non-Page Mode, the data is multiplexed with the lower address byte, and ALE is active in
every bus cycle. In Page Mode, data D[7:0] is multiplexed with address A[15:8]. In a bus
cycle where there is a Page hit, the ALE signal is not active and only addresses A[7:0]
are changing. The PSD813F supports both modes. In Page Mode, the PSD bus timing
is identical to Non-Page Mode except the address hold time and setup time with respect
to ALE is not required. The PSD access time is measured from address A[7:0] valid to
data in valid.
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