參數(shù)資料
型號: PSD612E1
英文描述: Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯,4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
中文描述: 現(xiàn)場可編程微控制器外圍設備和嵌入式微-細胞(可編程邏輯,4K的位的SRAM,26我個可編程輸入/輸出,通用PLD的有63個輸入)
文件頁數(shù): 67/84頁
文件大小: 426K
代理商: PSD612E1
PSD6XX Family
11-67
-70
-90
-15
PT
Aloc
Symbol
Parameter
Conditions
Min
Max
Min
Max
Min
Max
Unit
t
IS
Input Setup Time
(Note 2c)
0
0
0
ns
t
IH
Input Hold Time
(Note 2c)
20
22
26
ns
t
INH
NIB Input High Time
(Note 2c)
12
14
18
ns
t
INL
NIB Input Low Time
(Note 2c)
12
14
18
ns
t
INO
NIB Input to Combinatorial
Output Delay
(Note 2c)
46
51
59
Add 2
ns
Input Micro
Cell Timing
(5 V ± 10%)
NOTES:
2c.
Inputs from Port A, B and C relative to register/latch clock from the PLD. ALE latch timings refer to t
AVLX
and t
LXAX
.
PSD6XXE1 AC/DC Parameters – GPLD and ECSPLD Timing
(5 V ± 10% Versions)
相關PDF資料
PDF描述
PSD613E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯,4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
PSD703S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯,4K位SRAM,27個可編程I/O,通用PLD有66個輸入)
PSD701S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯,4K位SRAM,27個可編程I/O,通用PLD有66個輸入)
PSD702S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯,4K位SRAM,27個可編程I/O,通用PLD有66個輸入)
PSD711S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯,4K位SRAM,27個可編程I/O,通用PLD有66個輸入)
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