參數(shù)資料
型號： PSD612E1
英文描述： Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞（可編程邏輯，4K的位的SRAM，26我個可編程輸入/輸出，通用PLD的有63個輸入）
文件頁數(shù)： 29/84頁
文件大?。?/td> 426K
代理商： PSD612E1
PSD6XX Family
11-29
Bus Interface
(cont.)
80C251
The Intel 80C251 microcontroller features a user-configurable bus interface with four
possible bus configurations as shown in Table 18.
Configuration
80C251
Read/Write
Pins
Connecting
to PSD6XXE1
Pins
Page Mode
1
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Non-Page Mode, 80C31 compatible
A
[
7:0
]
multiplex with D
[
7:0
}
2
WR
PSEN only
CNTL0
CNTL1
Non-Page Mode
A
[
7:0
]
multiplex with D
[
7:0
}
3
WR
PSEN only
CNTL0
CNTL1
Page Mode
A
[
15:8
]
multiplex with D
[
7:0
}
4
WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Page Mode
A
[
15:8
]
multiplex with D
[
7:0
}
Table 18. 80C251 Configurations
Configuration 1 is 80C31 compatible. The bus interface to the PSD6XXE1 is identical to that
shown in Figure 12. Configurations 2 and 3 have the same bus connection as shown in
Figure 18 . There is only one read input (PSEN) connected to the CNTL1 pin on the
PSD6XXE1. The A16 connection to the PA0 pin allows for a larger address input to the
PSD6XXE1. Configuration 4 is shown in Figure 19. The RD signal is connected to CNTL 1
and the PSEN signal is connected to the CNTL2.
The 80C251 has two major operating modes: Page Mode and Non-Page Mode. In
Non-Page Mode, the data is multiplexed with the lower address byte. The ALE is active in
every bus cycle. In Page Mode, data D[7:0] is multiplexed with address A[15:8]. In a bus
cycle where there is a Page hit, the ALE signal is not active and only addresses A[7:0]
are changing. The PSD6XXE1 supports both modes. In Page Mode, the PSD bus timing is
identical to Non-Page Mode except the address hold time and setup time with respect to
ALE is not required. The PSD6XXE1 access time is measured from address A[7:0] valid to
data in valid.
Upon power up the 80C251 fetches locations at FFF8h and FFF9h where the bus
configuration bytes reside. After the configuration register is set, the 80C251 starts
executing codes from location 0000h. The 7th EPROM block in the PSD6XXE1 has two
chip selects, ES7A and ES7B. The second chip select, ES7B can be defined to occupy the
configuration byte locations while ES7A is assigned to a different memory space.
相關(guān)PDF資料
PDF描述
PSD613E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
PSD703S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入)
PSD701S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入)
PSD702S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD612E1-15J 制造商:WSI 功能描述:
PSD612E1-15JI 制造商:WSI 功能描述: 制造商:WSI 功能描述:64K X 8 OTPROM, 26 I/O, PIA-GENERAL PURPOSE, PQCC52
PSD612E1-70J 制造商:WSI 功能描述:
PSD612E1-70L 制造商:WSI 功能描述:
PSD612E1-90JI 制造商:WSI 功能描述:
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