參數(shù)資料
型號： PSD612E1
英文描述： Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞（可編程邏輯，4K的位的SRAM，26我個可編程輸入/輸出，通用PLD的有63個輸入）
文件頁數(shù)： 61/84頁
文件大小： 426K
代理商： PSD612E1
PSD6XX Family
11-61
Port Configuration
Reset
Power Down Mode
MCU I/O
Input
Unchanged
PLD Output
Active
Depends on inputs to the PLD
Address Out
Tri-stated
Not defined
Data Port
Tri-stated
Tri-stated
Peripheral I/O
Tri-stated
Tri-stated
Register
Reset
Power Down Mode
PMMR0 & 1
Cleared (power up reset)
Unchanged (warm reset)
Unchanged
Micro
Cells Flip-Flop
Unchanged*
Unchanged*
All other registers
Cleared to “0”
Unchanged
Table 34. Chip Status During Reset and Power Down Mode
Power
Management
Unit
(cont.)
*
The Micro
Cell Flip-Flop can be cleared or set by the reset input or the PDN (Power Down) signal, depending on
the .re and .pr equations that are defined in the PSDabel file.
Battery Backup
The PSD6XXE1 supports a battery backup operation that retains the contents of the
SRAM in the event of a power loss. The Port PC2 pin is dedicated as the input pin for an
external power source. If the supply voltage falls below a reference voltage (Vstby), an inter-
nal power-switch occurs so that PC2 provides power to the internal SRAM. The SRAM
contents are retained down to a level of 2V.
Security Protection
The PSD6XXE1 has a programmable security bit which acts as a duplication barrier.
When the bit is set, the contents of the EPROM, non-volatile configuration bits, and PLD
cannot be read by device programmers.
The security bit is set through the PSDsoft Software and is embedded in the compiled
output file. The security bit is UV erasable and a secured windowed part can be erased
and re-programmed.
相關(guān)PDF資料
PDF描述
PSD613E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
PSD703S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入)
PSD701S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入)
PSD702S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入)
PSD711S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD612E1-15J 制造商:WSI 功能描述:
PSD612E1-15JI 制造商:WSI 功能描述: 制造商:WSI 功能描述:64K X 8 OTPROM, 26 I/O, PIA-GENERAL PURPOSE, PQCC52
PSD612E1-70J 制造商:WSI 功能描述:
PSD612E1-70L 制造商:WSI 功能描述:
PSD612E1-90JI 制造商:WSI 功能描述:
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