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| 型號(hào)： | PSD612E1 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入) |
| 中文描述： | 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞（可編程邏輯，4K的位的SRAM，26我個(gè)可編程輸入/輸出，通用PLD的有63個(gè)輸入） |
| 文件頁(yè)數(shù)： | 10/84頁(yè) |
| 文件大?。?/td> | 426K |
| 代理商： | PSD612E1 |
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PSD6XX Family
11-10
PSD6XXE1
Architectural
Overview
(cont.)
Microcontroller Bus Interface
The PSD6XXE1 easily interfaces with most popular eight and sixteen-bit microcontrollers
with either multiplexed or non-multiplexed address/data busses. The device is configured to
respond to the microcontroller control signals which are also used as inputs to the PLDs.
Memory
The PSD6XXE1 contains EPROM and SRAM. The EPROM densities available are
256 Kbit, 512 Kbit and 1 Mbit. The space is divided into eight equally-sized blocks. Each
block can be located in a different address space defined by the user. The access time of
the EPROM includes the address latching and DPLD decoding.
The 4 Kbit SRAM may be used as a scratch pad memory and an extension of the
microcontroller SRAM. The SRAM data is retained in the event of a system power down,
provided a backup battery is connected to the Vstby pin (PC2). Switching from the V
CC
supply to standby power occurs automatically when V
CC
drops below Vstby voltage.
Page Register
The four-bit Page Register expands the address range of the microcontroller by sixteen
times. The paged address can be used as part of the address space to access external
memory and peripherals or internal EPROM, SRAM and I/O.
Power Management Unit
The Power Management Unit (PMU) in the PSD6XXE1 enables the user to control the
power consumption on selected functional blocks based on system requirements. The PMU
includes an Automatic Power Down unit (APD) that will turn off device functions due to
microcontroller inactivity in one of two modes: the Power Down mode and Sleep mode.
Other power saving features, such as the CMiser in the PMU, allow the EPROM/SRAM to
operate at a slower rate to conserve power.
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PDF描述 |
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| PSD613E1 | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入) |
| PSD703S5 | Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入) |
| PSD701S5 | Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入) |
| PSD702S5 | Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入) |
| PSD711S5 | Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個(gè)可編程I/O,通用PLD有66個(gè)輸入) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD612E1-15J | 制造商:WSI 功能描述: |
| PSD612E1-15JI | 制造商:WSI 功能描述: 制造商:WSI 功能描述:64K X 8 OTPROM, 26 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| PSD612E1-70J | 制造商:WSI 功能描述: |
| PSD612E1-70L | 制造商:WSI 功能描述: |
| PSD612E1-90JI | 制造商:WSI 功能描述: |
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