參數(shù)資料
型號： PSD612E1
英文描述： Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞（可編程邏輯，4K的位的SRAM，26我個可編程輸入/輸出，通用PLD的有63個輸入）
文件頁數(shù)： 44/84頁
文件大?。?/td> 426K
代理商： PSD612E1
PSD6XX Family
11-44
I/O Ports
(cont.)
Port Registers
(cont.)
Drive Register
The Drive Register configures the pin driver as Open Drain, or in the case of ECSPLD
outputs, sets the pin to operate in high slew rate. An external pull-up resistor is not required
when the pin is in the slew rate mode.
For Ports A and B the register sets different functions for the lower and higher nibbles. The
four upper bits set the corresponding bits the as CMOS (“0”) or Open Drain (“1”) driver. The
four lower bits are used for slew rate control. The slew rate is a measurement of the rise
and fall times of the output. A higher slew rate means a faster output response while a lower
slew rate is a slower, lower slope, response. The pin operates in high slew rate when the
corresponding bit in the Drive Register is set to “1”.
Table 25 shows the Drive Registers of Port A, B, C and D and which pin has the Open Drain
or Slew Rate configuration.
Drive
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port A
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port B
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port C
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
NA
Open
Drain
Open
Drain
Port D
NA
NA
NA
NA
NA
Slew
Rate
Slew
Rate
Slew
Rate
Table 25. Drive Register Pin Assignment
NOTE:
NA = Not Applicable, bit should set to “0”.
相關(guān)PDF資料
PDF描述
PSD613E1 Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
PSD703S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入)
PSD701S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入)
PSD702S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入)
PSD711S5 Field Programmable Microcontroller Peripherals with Supervisory Functions(可編程邏輯，4K位SRAM,27個可編程I/O,通用PLD有66個輸入)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD612E1-15J 制造商:WSI 功能描述:
PSD612E1-15JI 制造商:WSI 功能描述: 制造商:WSI 功能描述:64K X 8 OTPROM, 26 I/O, PIA-GENERAL PURPOSE, PQCC52
PSD612E1-70J 制造商:WSI 功能描述:
PSD612E1-70L 制造商:WSI 功能描述:
PSD612E1-90JI 制造商:WSI 功能描述:
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