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| 型號(hào)： | PIC18LF96J65-I/PT |
| 廠(chǎng)商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 95/131頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 48KX16 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | PIC® 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 41.667MHz |
| 連通性： | EBI/EMI，以太網(wǎng)，I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 70 |
| 程序存儲(chǔ)器容量： | 96KB（48K x 16） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| RAM 容量： | 3808 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 包裝： | 托盤(pán) |
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PIC18F97J60 FAMILY
DS39762F-page 66
2011 Microchip Technology Inc.
A CM Reset behaves similarly to a Master Clear Reset,
RESET
instruction, WDT time-out or Stack Event Reset.
As with all hard and power Reset events, the device
Configuration Words are reloaded from the Flash Con-
figuration Words in program memory as the device
restarts.
5.6
Power-up Timer (PWRT)
PIC18F97J60 family of devices incorporates an
on-chip Power-up Timer (PWRT) to help regulate the
Power-on Reset process. The PWRT is always
enabled. The main function is to ensure that the device
voltage is stable before code is executed.
The Power-up Timer (PWRT) of the PIC18F97J60 fam-
ily devices is an 11-bit counter which uses the INTRC
source as the clock input. This yields an approximate
time interval of 2048 x 32
s = 66 ms. While the PWRT
is counting, the device is held in Reset.
The power-up time delay depends on the INTRC clock
and will vary from chip-to-chip due to temperature and
process variation. See DC Parameter 33 for details.
5.6.1
TIME-OUT SEQUENCE
The PWRT time-out is invoked after the POR pulse has
cleared. The total time-out will vary based on the status
of the PWRT. Figure 5-3, Figure 5-4, Figure 5-5 and
Figure 5-6 all depict time-out sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the PWRT will expire. Bringing
MCLR
high
will
begin
execution
immediately
(Figure 5-5). This is useful for testing purposes or to
synchronize more than one PIC18FXXJ6X device
operating in parallel.
FIGURE 5-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
FIGURE 5-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
TPWRT
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
INTERNAL RESET
TPWRT
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
INTERNAL RESET
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