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參數(shù)資料
| 型號(hào)： | PIC18LF96J65-I/PT |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 79/131頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 48KX16 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | PIC® 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 41.667MHz |
| 連通性： | EBI/EMI，以太網(wǎng)，I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 70 |
| 程序存儲(chǔ)器容量： | 96KB（48K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 3808 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 包裝： | 托盤 |
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2011 Microchip Technology Inc.
DS39762F-page 51
PIC18F97J60 FAMILY
3.5
Internal Oscillator Block
The PIC18F97J60 family of devices includes an internal
oscillator source (INTRC) which provides a nominal
31 kHz output. The INTRC is enabled on device
power-up and clocks the device during its configuration
cycle until it enters operating mode. INTRC is also
enabled if it is selected as the device clock source or if
any of the following are enabled:
Fail-Safe Clock Monitor
Watchdog Timer
Two-Speed Start-up
These features are discussed in greater detail in
The INTRC can also be optionally configured as the
default clock source on device start-up by setting the
FOSC2 Configuration bit. This is discussed in
3.6
Ethernet Operation and the
Microcontroller Clock
Although devices of the PIC18F97J60 family can accept
a wide range of crystals and external oscillator inputs,
they must always have a 25 MHz clock source when
used for Ethernet applications. No provision is made for
internally generating the required Ethernet clock from a
primary oscillator source of a different frequency. A
frequency tolerance is specified, likely excluding the use
of ceramic resonators. See Section 28.0 “Electrical
, Table 28-6, Parameter 5, for more
details.
3.6.1
PLL BLOCK
To accommodate a range of applications and micro-
controller clock speeds, a separate PLL block is
incorporated into the clock system. It consists of three
components:
A configurable prescaler (1:2 or 1:3)
A 5x PLL frequency multiplier
A configurable postscaler (1:1, 1:2, or 1:3)
The operation of the PLL block’s components is
controlled by the OSCTUNE register (Register 3-1).
The use of the PLL block’s prescaler and postscaler,
with or without the PLL itself, provides a range of
system clock frequencies to choose from, including the
unaltered 25 MHz of the primary oscillator. The full
range of possible oscillator configurations compatible
with Ethernet operation is shown in Table 3-2.
REGISTER 3-1:
OSCTUNE: PLL BLOCK CONTROL REGISTER
R/W-0
U-0
PPST1
PLLEN(1)
PPST0
PPRE
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
PPST1:
PLL Postscaler Configuration bit
1
= Divide-by-2
0
= Divide-by-3
bit 6
PLLEN:
5x Frequency Multiplier PLL Enable bit(1)
1
= PLL is enabled
0
= PLL is disabled
bit 5
PPST0:
PLL Postscaler Enable bit
1
= Postscaler is enabled
0
= Postscaler is disabled
bit 4
PPRE:
PLL Prescaler Configuration bit
1
= Divide-by-2
0
= Divide-by-3
bit 3-0
Unimplemented:
Read as ‘0’
Note 1:
Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and is read
as ‘0’.
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