參數(shù)資料
型號: PIC16C554-04/P
廠商: Microchip Technology
文件頁數(shù): 58/108頁
文件大?。?/td> 0K
描述: IC MCU OTP 512X14 18DIP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 25
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 13
程序存儲器容量: 896B(512 x 14)
程序存儲器類型: OTP
RAM 容量: 80 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 18-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁面: 635 (CN2011-ZH PDF)
配用: ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
309-1059-ND - ADAPTER 18 ZIF BD W/18SO PLUGS
DVA16XP180-ND - ADAPTER DEVICE FOR MPLAB-ICE
AC164010-ND - MODULE SKT PROMATEII DIP/SOIC
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 51
PIC16C55X
7.3.1
SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
program execution). To avoid an unintended device
RESET,
the
following
instruction
sequence
(Example 7-1) must be executed when changing the
prescaler assignment from Timer0 to WDT. Lines 5-7
are required only if the desired postscaler rate is 1:1
(PS<2:0> = 000) or 1:2 (PS<2:0> = 001).
EXAMPLE 7-1:
CHANGING PRESCALER
(TIMER0
→WDT)
To change prescaler from the WDT to the TMR0
module use the sequence shown in Example 7-2. This
precaution must be taken even if the WDT is disabled.
EXAMPLE 7-2:
CHANGING PRESCALER
(WDT
→TIMER0)
TABLE 7-1:
REGISTERS ASSOCIATED WITH TIMER0
BCF
STATUS, RP0 ;Skip if already in
;Bank 0 CLRWDT Clear WDT
CLRF
TMR0
;Clear TMR0 & Prescaler
BSF
STATUS, RP0 ;Bank 1
MOVLW
'00101111’b ;These 3 lines (5, 6, 7)
MOVWF
OPTION
;Are required only if
;Desired PS<2:0> are
;CLRWDT 000 or 001
MOVLW
'00101xxx’b ;Set Postscaler to
MOVWF
OPTION
;Desired WDT rate
BCF
STATUS, RP0 ;Return to Bank 0
CLRWDT
;Clear WDT and
;prescaler
BSF
STATUS, RP0
MOVLW
b'xxxx0xxx'
;Select TMR0, new
;prescale value and
;clock source
MOVWF
OPTION
BCF
STATUS, RP0
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
All Other
RESETS
01h
TMR0
Timer0 module’s register
xxxx xxxx
uuuu uuuu
0Bh/8Bh
INTCON
GIE
Reserved
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
81h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
85h
TRISA
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
---1 1111
Legend:
— = Unimplemented locations, read as ‘0’,
Note
1:
Shaded bits are not used by TMR0 module.
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