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| 型號： | PIC16C554-04/P |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 49/108頁 |
| 文件大小： | 0K |
| 描述： | IC MCU OTP 512X14 18DIP |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 系列： | PIC® 16C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 13 |
| 程序存儲器容量： | 896B（512 x 14） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 80 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 18-DIP（0.300"，7.62mm） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 635 (CN2011-ZH PDF) |
| 配用： | ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING 309-1059-ND - ADAPTER 18 ZIF BD W/18SO PLUGS DVA16XP180-ND - ADAPTER DEVICE FOR MPLAB-ICE AC164010-ND - MODULE SKT PROMATEII DIP/SOIC |
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2002 Microchip Technology Inc.
Preliminary
DS40143D-page 43
PIC16C55X
6.6
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt (e.g., W register and STATUS
register). This will have to be implemented in software.
Example 6-1 stores and restores the STATUS and W
registers. The user register,
W_TEMP, must be defined
in both banks and must be defined at the same offset
from the bank base address (i.e.,
W_TEMP is defined at
0x20 in Bank 0 and it must also be defined at 0xA0 in
Bank 1). The user register,
STATUS_TEMP, must be
defined in Bank 0. The Example 6-1:
Stores the W register
Stores the STATUS register in Bank 0
Executes the ISR code
Restores the STATUS (and bank select bit
register)
Restores the W register
EXAMPLE 6-1:
SAVING THE STATUS
AND W REGISTERS IN
RAM
6.7
Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscil-
lator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the CLKIN pin. That means that the WDT will run, even
if the clock on the OSC1 and OSC2 pins of the device
has been stopped, for example, by execution of a
SLEEP
instruction. During normal operation, a WDT
timeout generates a device RESET. If the device is in
SLEEP mode, a WDT timeout causes the device to
wake-up and continue with normal operation. The WDT
can be permanently disabled by programming the con-
figuration bit WDTE as clear (Section 6.1).
6.7.1
WDT PERIOD
The WDT has a nominal timeout period of 18 ms, (with
no prescaler). The timeout periods vary with tempera-
ture, V
DD and process variations from part-to-part (see
DC specs). If longer timeout periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, timeout periods up to 2.3
seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer timeout.
6.7.2
WDT PROGRAMMING
CONSIDERATIONS
It should also be taken in account that under worst case
conditions (V
DD = Min., Temperature = Max., max.
WDT prescaler) it may take several seconds before a
WDT timeout occurs.
MOVWF
W_TEMP
;copy W to TEMP
;register, could be in
;either bank
SWAPF
STATUS,W
;swap STATUS to be
;saved into W
BCF
STATUS,RP0
;change to bank0
;regardless of
;current bank
MOVWF
STATUS_TEMP
;save STATUS to bank0
;register
:
SWAPF
STATUS_TEMP,W ;swap STATUS_TEMP
;register into W, sets
;bank to original state
MOVWF
STATUS
;move W into STATUS
;register
SWAPF
W_TEMP,F
;swap W_TEMP
SWAPF
W_TEMP,W
;swap W_TEMP into W
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