參數(shù)資料
型號(hào)： PIC16C554-04/P
廠商： Microchip Technology
文件頁(yè)數(shù)： 25/108頁(yè)
文件大?。?/td> 0K
描述： IC MCU OTP 512X14 18DIP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 25
系列： PIC® 16C
核心處理器： PIC
芯體尺寸： 8-位
速度： 4MHz
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 13
程序存儲(chǔ)器容量： 896B（512 x 14）
程序存儲(chǔ)器類(lèi)型： OTP
RAM 容量： 80 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 18-DIP（0.300"，7.62mm）
包裝： 管件
產(chǎn)品目錄頁(yè)面： 635 (CN2011-ZH PDF)
配用： ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
309-1059-ND - ADAPTER 18 ZIF BD W/18SO PLUGS
DVA16XP180-ND - ADAPTER DEVICE FOR MPLAB-ICE
AC164010-ND - MODULE SKT PROMATEII DIP/SOIC
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 21
PIC16C55X
4.3
PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high bits (PC<12:8>) are not
directly readable or writable and come from PCLATH.
On any RESET, the PC is cleared. Figure 4-6 shows
the two situations for the loading of the PC. The upper
example in the figure shows how the PC is loaded on a
write to PCL (PCLATH<4:0>
→ PCH). The lower exam-
ple in Figure 4-6 shows how the PC is loaded during a
CALL or GOTO instruction (PCLATH<4:3> → PCH).
FIGURE 4-6:
LOADING OF PC IN
DIFFERENT SITUATIONS
4.3.1
COMPUTED GOTO
A computed
GOTO is accomplished by adding an offset
to the program counter (
ADDWF PCL). When doing a
table read using a computed
GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
4.3.2
STACK
The PIC16C55X family has an 8-level deep x 13-bit
wide hardware stack (Figure 4-1 and Figure 4-2). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a
CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a
RETURN, RETLW or a RET-
FIE instruction execution. PCLATH is not affected by a
PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
4.4
Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses data pointed to by the file select register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a no-
operation (although status bits may be affected). An
effective 9-bit address is obtained by concatenating the
8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 4-7. However, IRP is not used in the
PIC16C55X.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-1.
EXAMPLE 4-1:
INDIRECT ADDRESSING
PC
12
8
7
0
5
PCLATH<4:0>
PCLATH
Instruction with
ALU result
GOTO, CALL
Opcode <10:0>
8
PC
12
11 10
0
11
PCLATH<4:3>
PCH
PCL
87
2
PCLATH
PCH
PCL
PCL as
Destination
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or vectoring to an interrupt
address.
movlw
0x20
;initialize pointer
movwf
FSR
;to RAM
NEXT
clrf
INDF
;clear INDF register
incf
FSR
;inc pointer
btfss
FSR,4
;all done?
goto
NEXT
;no clear next
;yes continue
CONTINUE:
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