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參數(shù)資料
| 型號(hào)： | PIC12F506 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 8/14-Pin, 8-Bit Flash Microcontroller |
| 中文描述： | 8/14-Pin，8位閃存微控制器 |
| 文件頁(yè)數(shù)： | 96/116頁(yè) |
| 文件大?。?/td> | 907K |
| 代理商： | PIC12F506 |
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PIC12F510/16F506
DS41268C-page 94
Preliminary
2007 Microchip Technology Inc.
TABLE 13-7:
TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40
°
C
≤
T
A
≤
+85
°
C (industrial)
-40
°
C
≤
T
A
≤
+125
°
C (extended)
FIGURE 13-8:
RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING
AC CHARACTERISTICS
Param
No.
Sym
Characteristic
Min
Typ
(1)
Max
Units
17
18
T
OS
H2
IO
V
T
OS
H2
IO
I
OSC1
↑
(Q1 cycle) to Port out valid
(2), (3)
OSC1
↑
(Q2 cycle) to Port input invalid
(I/O in hold time)
(2)
Port input valid to OSC1
↑
(I/O in setup time)
Port output rise time
(2), (3)
Port output fall time
(2), (3)
These parameters are characterized but not tested.
** These parameters are design targets and are not tested.
Note 1:
Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for
design guidance only and are not tested.
2:
Measurements are taken in EXTRC mode.
3:
See Figure 13-5 for loading conditions.
—
TBD
—
—
100*
—
ns
ns
19
20
21
T
IO
V2
OS
H
T
IO
R
T
IO
F
TBD
—
—
—
10
10
—
25**
25**
ns
ns
ns
*
V
DD
MCLR
Internal
POR
DRT
Timeout
(2)
Internal
Reset
Watchdog
Timer Reset
32
31
34
I/O pin
(1)
32
32
34
30
Note
1:
2:
I/O pins must be taken out of High-Impedance mode by enabling the output drivers in software.
Runs in MCLR or WDT Reset only in XT, LP and HS modes.
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