
PI7C9X7952
PCI Express Dual UART
Datasheet
Page 45 of 68
May 2013 – Revision 1.4
Pericom Semiconductor
7.1.6.
LINE CONTROL REGISTER – OFFSET 03h
BIT
FUNCTION
TYPE
DESCRIPTION
1:0
Data Length
RW
00b: 5-bit data length
01b: 6-bit data length
10b: 7-bit data length
11b: 8-bit data length
Reset to 11b.
2
Stop-Bit Length
RW
Bit 2 value
Data length
Stop bit length
0
5,6,7,8
1
5
1.5
1
6,7,8
2
Reset to 0b.
5:3
Parity Type
RW
Bit 5
Bit 4
Bit 3
Parity selection
X
0
No parity
0
1
Odd parity
0
1
Even parity
1
0
1
Mark
1
Space
Reset to 000b.
6
Transmission
Break
RW
0b: No transmit break condition
1b: Force the transmitter output to a space for alerting the remote
receiver of a line break condition.
Reset to 0b.
7
Divisor Latch
Enable
RW
0b: Data registers are selected
1b: Divisor latch registers are selected
Reset to 0b.
7.1.7.
MODEM CONTROL REGISTER – OFFSET 04h
BIT
FUNCTION
TYPE
DESCRIPTION
0
DTR Pin Control
RW
0b: Forces DTR output high
1b: Forces DTR output low
Reset to 0b.
1
RTS Pin Control
RW
0b: Forces RTS output high
1b: Forces RTS output low
Reset to 0b.
2
Output 1
RW
When the Internal Loopback Mode is enabled by setting Modem
Control Register Bit[4], output of the Output1 is routed to RI.
Reset to 0b.
3
Output 2
RW
When the Internal Loopback Mode is enabled by setting Modem
Control Register Bit[4], output of the Output2 is routed to DCD.
Reset to 0b.
4
Internal Loopback
Mode
RW
0b: Disables Internal Loopback Mode
1b: Enables Internal Loopback Mode
Reset to 0b.
13-0092