
PI7C9X7952
PCI Express Dual UART
Datasheet
Page 4 of 68
May 2013 – Revision 1.4
Pericom Semiconductor
Table of Contents
1.
FEATURES ............................................................................................................................................9
2.
APPLICATIONS ...................................................................................................................................9
3.
GENERAL DESCRIPTION ...............................................................................................................10
4.
PIN ASSIGNMENT.............................................................................................................................11
4.1.
PIN LIST OF 128-PIN LQFP..........................................................................................................11
4.2.
PIN DESCRIPTION ......................................................................................................................12
4.2.1.
UART INTERFACE................................................................................................................12
4.2.2.
PCI EXPRESS INTERFACE ..................................................................................................13
4.2.3.
SYSTEM INTERFACE............................................................................................................13
4.2.4.
TEST SIGNALS......................................................................................................................14
4.2.5.
EEPROM INTERFACE..........................................................................................................15
4.2.6.
POWER PINS ........................................................................................................................15
5.
FUNCTIONAL DESCRIPTION ........................................................................................................16
5.1.
CONFIGURATION SPACE ..........................................................................................................16
5.1.1.
PCI Express Configuration Space .........................................................................................16
5.1.2.
UART Configuration Space ...................................................................................................16
5.2.
DEVICE OPERATION..................................................................................................................17
5.2.1.
Configuration Access.............................................................................................................17
5.2.2.
I/O Reads/Writes....................................................................................................................17
5.2.3.
Memory Reads/Writes ............................................................................................................17
5.2.4.
Mode Selection ......................................................................................................................18
5.2.5.
450/550 Mode ........................................................................................................................18
5.2.6.
Enhanced 550 Mode ..............................................................................................................18
5.2.7.
Enhanced 950 Mode ..............................................................................................................18
5.2.8.
Transmit and Receive FIFOs .................................................................................................18
5.2.9.
Automated Flow Control........................................................................................................20
5.2.10.
Internal Loopback..................................................................................................................21
5.2.11.
Crystal Oscillator ..................................................................................................................22
5.2.12.
Baud Rate Generation ...........................................................................................................23
5.2.13.
Power Management ...............................................................................................................23
6.
PCI EXPRESS REGISTER DESCRIPTION ...................................................................................24
6.1.
REGISTER TYPES .......................................................................................................................24
6.2.
CONFIGURATION REGISTERS.................................................................................................24
6.2.1.
VENDOR ID REGISTER – OFFSET 00h ..............................................................................25
6.2.2.
DEVICE ID REGISTER – OFFSET 00h................................................................................25
6.2.3.
COMMAND REGISTER – OFFSET 04h...............................................................................25
6.2.4.
STATUS REGISTER – OFFSET 04h......................................................................................25
6.2.5.
REVISION ID REGISTER – OFFSET 08h ............................................................................26
6.2.6.
CLASS CODE REGISTER – OFFSET 08h............................................................................26
6.2.7.
CACHE LINE REGISTER – OFFSET 0Ch............................................................................26
6.2.8.
MASTER LATENCY TIMER REGISTER – OFFSET 0Ch .....................................................26
6.2.9.
HEADER TYPE REGISTER – OFFSET 0Ch.........................................................................27
6.2.10.
BASE ADDRESS REGISTER 0 – OFFSET 10h.....................................................................27
6.2.11.
BASE ADDRESS REGISTER 1 – OFFSET 14h.....................................................................27
6.2.12.
SUBSYSTEM VENDOR REGISTER – OFFSET 2Ch ............................................................27
6.2.13.
SUBSYSTEM ID REGISTER – OFFSET 2Ch........................................................................27
13-0092