- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄1962 > PI7C9X7952AFDE (Pericom)IC PCIE-TO-UART BRIDGE 128LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | PI7C9X7952AFDE |
| 廠(chǎng)商： | Pericom |
| 文件頁(yè)數(shù)： | 36/68頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PCIE-TO-UART BRIDGE 128LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 應(yīng)用： | PCIe至UART橋接 |
| 接口： | 高級(jí)配置電源接口（ACPI） |
| 電源電壓： | 1.8V, 3.3V |
| 封裝/外殼： | 128-LQFP 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x14） |
| 包裝： | 托盤(pán) |
| 安裝類(lèi)型： | 表面貼裝 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)當(dāng)前第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)
PI7C9X7952
PCI Express Dual UART
Datasheet
Page 41 of 68
May 2013 – Revision 1.4
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
11:9
Reserved
RO
Reset to 000b.
12
Replay Timer
Timeout Mask
RWS
When set, the Replay Timer Timeout event is not logged in the
Header Log register and not issued as an Error Message to RC
either.
Reset to 0b.
31:13
Reserved
RO
Reset to 00000h .
6.2.64. ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h
BIT
FUNCTION
TYPE
DESCRIPTION
4:0
First Error Pointer
ROS
It indicates the bit position of the first error reported in the
Uncorrectable Error Status register.
Reset to 00000b.
5
ECRC Generation
Capable
RO
When set, it indicates the I/O bridge has the capability to generate
ECRC.
Reset to 1b.
6
ECRC Generation
Enable
RWS
When set, it enables the generation of ECRC when needed.
Reset to 0b.
7
ECRC Check
Capable
RO
When set, it indicates the I/O bridge has the capability to check
ECRC.
Reset to 1b.
8
ECRC Check
Enable
RWS
When set, the function of checking ECRC is enabled.
Reset to 0b.
31:9
Reserved
RO
Reset to 000000h.
6.2.65. HEADER LOG REGISTER – OFFSET From 11Ch to 128h
BIT
FUNCTION
TYPE
DESCRIPTION
3:0
1st DWORD
RO
Hold the 1st DWORD of TLP Header. The Head byte is in big
endian.
7:4
2nd DWORD
RO
Hold the 2nd DWORD of TLP Header. The Head byte is in big
endian.
11:8
3rd DWORD
RO
Hold the 3rd DWORD of TLP Header. The Head byte is in big
endian.
15:12
4th DWORD
RO
Hold the 4th DWORD of TLP Header. The Head byte is in big
endian.
13-0092
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C9X7954AFDE | IC PCIE-TO-UART BRIDGE 128LQFP |
| PI7C9X7958ANBE | IC PCIE-TO-UART BRIDGE 160LFBGA |
| PI90LV017AUEX | IC LVDS DIFF LINE DVR 3V 8-MSOP |
| PI90LV01TEX | IC LVDS DIFF LINE DRVR SOT23-5 |
| PI90LV027AW | IC DUAL LVDS LINE DRIVER 8-SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C9X7952AFDEX | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C9X7954AEVB | 制造商:Pericom Semiconductor Corporation 功能描述:EVAL BOARD PI7C9X7954/52A |
| PI7C9X7954AFDE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI X1 PCIE-UART 4 Channel Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X7958AEVB | 制造商:Pericom Semiconductor Corporation 功能描述:7958A EVAL BOARD 制造商:Pericom Semiconductor Corporation 功能描述:EVAL BOARD PI7C9X7958A 制造商:Pericom Semiconductor Corporation 功能描述:8 Port PCI Express UART I/O Bridge Evaluation Board |
| PI7C9X7958ANBE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI X1 PCIE-UART 8 Channel Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。