Pericom Semiconductor 31 – 24 23 – 16 15 – 8 7 – 0 BYTE OFFSET" />
參數(shù)資料
型號： PI7C9X7952AFDE
廠商： Pericom
文件頁數(shù)： 18/68頁
文件大?。?/td> 0K
描述： IC PCIE-TO-UART BRIDGE 128LQFP
標(biāo)準(zhǔn)包裝： 90
應(yīng)用： PCIe至UART橋接
接口： 高級配置電源接口（ACPI）
電源電壓： 1.8V, 3.3V
封裝/外殼： 128-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 128-LQFP（14x14）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X7952
PCI Express Dual UART
Datasheet
Page 25 of 68
May 2013 – Revision 1.4
Pericom Semiconductor
31 – 24
23 – 16
15 – 8
7 – 0
BYTE OFFSET
Correctable Error Mask Register
114h
Advanced Error Capabilities and Control Register
118h
Header Log Register
11Ch~128h
6.2.1.
VENDOR ID REGISTER – OFFSET 00h
BIT
FUNCTION
TYPE
DESCRIPTION
15:0
Vendor ID
RO
Identifies Pericom as the vendor of this device. The register is
hardwired as 12D8h.
6.2.2.
DEVICE ID REGISTER – OFFSET 00h
BIT
FUNCTION
TYPE
DESCRIPTION
31:16
Device ID
RO
Identifies this device as the PI7C9X7952. Reset to 7952h.
6.2.3.
COMMAND REGISTER – OFFSET 04h
BIT
FUNCTION
TYPE
DESCRIPTION
0
I/O Space Enable
RW
Controls a device’s response to I/O Space accesses. A value of 0
disables the device response. A value of 1 allows the device to
respond to I/O Space accesses.
Reset to 0b.
1
Memory Space
Enable
RW
Controls a device’s response to Memory Space accesses. A value of 0
disables the device response. A value of 1 allows the device to
response to memory Space accesses.
Reset to 0b.
2
Bus Master Enable
RO
It is not implemented. Hardwired to 0b.
3
Special Cycle
Enable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
4
Memory Write And
Invalidate Enable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
5
VGA Palette Snoop
Enable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
6
Parity Error
Response Enable
RW
Controls the device’s response to parity errors. When the bit is set,
the device must take its normal action when a parity error is
detected. When the bit is 0, the device sets its Detected Parity Error
Status bit when an error is detected.
Reset to 0b.
7
Wait Cycle Control
RO
Does not apply to PCI Express. Must be hardwired to 0b.
8
SERR# enable
RW
This bit, when set, enables reporting of Non-fatal and Fatal errors
detected by the device to the Root Complex.
Reset to 0b.
9
Fast Back-to-Back
Enable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
10
Interrupt Disable
RW
Controls the ability of the I/O bridge to generate INTx interrupt
Messages.
Reset to 0b.
15:11
Reserved
RO
Reset to 00000b.
6.2.4.
STATUS REGISTER – OFFSET 04h
BIT
FUNCTION
TYPE
DESCRIPTION
18:16
Reserved
RO
Reset to 000b.
19
Interrupt Status
RO
Indicates that an INTx interrupt Message is pending internally to the
device.
13-0092
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C9X7952AFDEX 制造商:Pericom Semiconductor Corporation 功能描述:
PI7C9X7954AEVB 制造商:Pericom Semiconductor Corporation 功能描述:EVAL BOARD PI7C9X7954/52A
PI7C9X7954AFDE 功能描述:外圍驅(qū)動器與原件 - PCI X1 PCIE-UART 4 Channel Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X7958AEVB 制造商:Pericom Semiconductor Corporation 功能描述:7958A EVAL BOARD 制造商:Pericom Semiconductor Corporation 功能描述:EVAL BOARD PI7C9X7958A 制造商:Pericom Semiconductor Corporation 功能描述:8 Port PCI Express UART I/O Bridge Evaluation Board
PI7C9X7958ANBE 功能描述:外圍驅(qū)動器與原件 - PCI X1 PCIE-UART 8 Channel Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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