
PI7C9X7952
PCI Express Dual UART
Datasheet
Page 27 of 68
May 2013 – Revision 1.4
Pericom Semiconductor
6.2.9.
HEADER TYPE REGISTER – OFFSET 0Ch
BIT
FUNCTION
TYPE
DESCRIPTION
23:16
Header Type
RO
Read as 00h to indicate that the register layout conforms to the
standard PCI-to-PCI bridge layout.
6.2.10. BASE ADDRESS REGISTER 0 – OFFSET 10h
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
Base Address 0
RW
Use this I/O base address to map the UART 16550 compatible
registers.
The base address can be allocated to 64 Bytes.
Reset to 00000001h.
6.2.11. BASE ADDRESS REGISTER 1 – OFFSET 14h
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
Base Address 1
RW
Use this memory base address to map the UART 16550 compatible
and enhanced registers.
The base address can be allocated to 4096 Bytes.
Reset to 00000000h
6.2.12. SUBSYSTEM VENDOR REGISTER – OFFSET 2Ch
BIT
FUNCTION
TYPE
DESCRIPTION
15:0
Sub Vendor ID
RO
Indicates the sub-system vendor id. The default value may be
changed by auto-loading from EEPROM.
Reset to 0000h.
6.2.13. SUBSYSTEM ID REGISTER – OFFSET 2Ch
BIT
FUNCTION
TYPE
DESCRIPTION
31:16
Sub System ID
RO
Indicates the sub-system device id. The default value may be
changed by auto-loading from EEPROM.
Reset to 0000h.
6.2.14. CAPABILITIES POINTER REGISTER – OFFSET 34h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Capabilities Pointer
RO
This optional register points to a linked list of new capabilities
implemented by the device. This default value may be changed by
auto-loading from EEPROM.
The default value is 80h.
6.2.15. INTERRUPT LINE REGISTER – OFFSET 3Ch
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Interrupt Line
RW
Used to communicate interrupt line routing information. POST
software will write the routing information into this register as it
initializes and configures the system.
Reset to 00h.
13-0092