
PI7C9X7952
PCI Express Dual UART
Datasheet
Page 31 of 68
May 2013 – Revision 1.4
Pericom Semiconductor
6.2.33. NEXT ITEM POINTER REGISTER – OFFSET A4h
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Next Item Pointer
RO
The pointer points to the PCI Express capability register (E0h).
Reset to E0h.
6.2.34. LENGTH REGISTER – OFFSET A4h
BIT
FUNCTION
TYPE
DESCRIPTION
31:16
Length Information
RO
The length field provides the information for number of bytes in the
capability structure (including the ID and Next pointer bytes).
Reset to 28h.
6.2.35. XPIP CSR0 – OFFSET A8h (Test Purpose Only)
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
Reserved
RW
Reset to 04001060h.
6.2.36. XPIP CSR1 – OFFSET ACh (Test Purpose Only)
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
Reserved
RW
Reset to 004000271h.
6.2.37. REPLAY TIME-OUT COUNTER – OFFSET B0h
BIT
FUNCTION
TYPE
DESCRIPTION
11:0
User Replay Timer
RW
A 12-bit register contains a user-defined value. The default value
may be changed by auto-loading from EEPROM.
Reset to 000h.
12
Enable User Replay
Timer
RW
When asserted, the user-defined replay time-out value would be
employed. The default value may be changed by auto-loading from
EEPROM.
Reset to 0b.
15:13
Reserved
RO
Reset to 000b.
6.2.38. ACKNOWLEDGE LATENCY TIMER – OFFSET B0h
BIT
FUNCTION
TYPE
DESCRIPTION
29:16
User ACK Latency
Timer
RW
A 14-bit register contains a user-defined value. The default value
may be changed by auto-loading from EEPROM.
Reset to 0000h..
30
Enable User ACK
Latency
RW
When asserted, the user-defined ACK latency value would be
employed. The default value may be changed by auto-loading from
EEPROM.
Reset to 0b.
31
Reserved
RO
Reset to 0b.
6.2.39. UART DRIVE SETTING – OFFSET B4h
BIT
FUNCTION
TYPE
DESCRIPTION
3:0
UART 0
Transmitter Driver
Enable
RW
UART 0 DRIVER. The default value may be changed by
auto-loading from EEPROM.
13-0092