- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368020 > PI7C7100 (Pericom Semiconductor Corp.) 3-Port PCI Bridge PDF資料下載
參數(shù)資料
| 型號： | PI7C7100 |
| 廠商： | Pericom Semiconductor Corp. |
| 英文描述： | 3-Port PCI Bridge |
| 中文描述： | 3端口PCI橋 |
| 文件頁數(shù)： | 36/132頁 |
| 文件大?。?/td> | 2559K |
| 代理商： | PI7C7100 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當前第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁
28
09/18/00 Rev 1.1
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456
5. Address Decoding
PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
PI7C7100 uses three address ranges that control I/O and memory transaction forwarding. These address ranges are
defined by base and limit address registers in the configuration space. This chapter describes these address ranges,
as well as ISA-
mode and VGA-addressing support.
5.1 Address Ranges
PI7C7100 uses the following address ranges that determine which I/O and memory transactions are forwarded from
the primary PCI bus to the secondary PCI bus, and from the secondary bus to the primary bus:
Two 32-bit I/O address ranges
Two 32-bit memory-mapped I/O (non-prefetchable memory) ranges
Two 32-bit prefetchable memory address ranges
Transactions falling within these ranges are forwarded downstream from the primary PCI bus to the two secondary PCI
buses. Transactions falling outside these ranges are forwarded upstream from the two secondary PCI buses to the
primary PCI bus.
No address translation is required in PI7C7100. The addresses that are not marked for downstream are always
forwarded upstream. However, if an address of a transaction initiated from S1 bus is located in the marked address
range for downstream in S2 bus and not in the marked address range for downstream in S1 bus, the transaction will
be forwarded to S2 bus instead of primary bus. By the same token, if an address of a transaction initiated from S2 bus
is located in the marked address range for downstream in S1 bus and not in the marked address range for downstream
in S2 bus, the transaction will be forwarded to S1 bus instead of primary bus.
5.2 I/O Address Decoding
PI7C7100 uses the following mechanisms that are defined in the configuration space to specify the I/O address space
for downstream and upstream forwarding:
I/O base and limit address registers
The ISA enable bit
The VGA mode bit
The VGA snoop bit
This section provides information on the I/O address registers and ISA mode.
Section 5.4 provides information on the VGA modes.
To enable downstream forwarding of I/O transactions, the I/O enable bit must be set in the command register in
configuration space. All I/O transactions initiated on the primary bus will be ignored if the I/O enable bit is not set. To
enable upstream forwarding of I/O transactions, the master enable bit must be set in the command register. If the master-
enable bit is not set, PI7C7100 ignores all I/O and memory transactions initiated on the secondary bus. The master-
enable bit also allows upstream forwarding of memory transactions if it is set.
CAUTION
If any configuration state affecting I/O transaction forwarding is changed by a configuration write
operation on the primary bus at the same time that I/O transactions are ongoing on the secondary bus,
PI7C7100 response to the secondary bus I/O transactions is not predictable. Configure the I/O base and
limit address registers, SA enable bit, VGA mode bit, and VGA snoop bit before setting I/O enable and master
enable bits, and change them subsequently only when the primary and secondary PCI buses are idle.
5.2.1 I/O Base and Limit Address Registers
PI7C7100 implements one set of I/O base and limit address registers in configuration space that define an I/O address
range per port downstream forwarding. PI7C7100 supports 32-bit I/O addressing, which allows I/O addresses
downstream of PI7C7100 to be mapped anywhere in a 4GB I/O address space.
相關PDF資料 |
PDF描述 |
|---|---|
| PI7C7100CNA | 3-Port PCI Bridge |
| PI7C7300 | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300ANA | 3-PORT PCI-to-PCI BRIDGE |
| PI7C8140A | 2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C7100BNA | 制造商:Pericom Semiconductor Corporation 功能描述:3 PORT PCI TO PCI |
| PI7C7100CNA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-Port PCI Bridge |
| PI7C7300 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300AEVB-3 | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
發(fā)布緊急采購，3分鐘左右您將得到回復。