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參數資料
| 型號： | PHASE-LOCKEDLOOP |
| 元件分類： | 串行ADC |
| 英文描述： | Micropower Sampling 8-Bit Serial I/O A/D Converters; Package: SO; No of Pins: 8; Temperature Range: -40°C to +85°C |
| 中文描述： | 壓控Ocillator |
| 文件頁數： | 9/20頁 |
| 文件大?。?/td> | 1757K |
| 代理商： | PHASE-LOCKEDLOOP |
Revision 1.01/April 2002 Semtech Corp.
Page 9
www.semtech.com
AN-SETS-7
ADVANCED COMMUNICATIONS
APPLICATION NOTE
PLL Configurations for ACS8530
2.3
Default Configuration for Independent T4 and T0 Paths
The default configuration for the ACS8530 for the T0 and T4 paths to produce simultaneous
independent clock outputs is shown in Figure 5.
This configuration will yield high jitter BITS/AMI clocks from the T4 path. In addition, the T4 APLL will yield
low jitter
OC-N clocks. The T0 path will yield low jitter OC-N, clocks and high jitter n x E1/DS1 simultaneously.
Figure 5
Default configuration of the T0 and T4 PLLs for simultaneous clock output.
The register settings for the default configuration are as follows:
Reg 35 bit 7 = 0
Reg 35 bit 6 = 1
Reg 35 bit 4 = 0
Reg 64 bit (2:0) = 001, see Table 3
Reg 65 bit 7 = 0
Reg 65 bit 6 = 0
Reg 65 bit (5:4) = 00
Reg 65 bit (2:0) = 000, see Table 2
Must use
LOCK8K
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