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參數資料
| 型號： | PHASE-LOCKEDLOOP |
| 元件分類： | 串行ADC |
| 英文描述： | Micropower Sampling 8-Bit Serial I/O A/D Converters; Package: SO; No of Pins: 8; Temperature Range: -40°C to +85°C |
| 中文描述： | 壓控Ocillator |
| 文件頁數： | 7/20頁 |
| 文件大小： | 1757K |
| 代理商： | PHASE-LOCKEDLOOP |
Revision 1.01/April 2002 Semtech Corp.
Page 7
www.semtech.com
AN-SETS-7
ADVANCED COMMUNICATIONS
APPLICATION NOTE
PLL Configurations for ACS8530
The T4 path is much simpler than the T0 path - see Figure 3. This path offers no Phase Build-out or phase
offset. The T4 input can be used to either lock to a reference clock input independent of the T0 path, or
lock to the T0 path. Unlike the T0 path, the T4 forward DFS block does not always generate 77.76 MHz.
The possible frequencies are listed in Appendix description for Register 64. Similarly to the T0 path, the
output of the T4 forward DFS block is generated using DFS clocked by the 204.8 MHz system clock and
will have an inherent jitter of 4.9 ns. The T4 feedback DFS also has the facility to be able to use the post
APLL (jitter-filtered) clock to generate the feedback locking frequency. Again, this will give the maximum
performance by using a low jitter feedback, see Figure 4. The T4 output APLL block is also for multiplying
and filtering. The input to the T4 output APLL can come either from the T4 forward DFS block or from the
T0 path. These configurations are described in more detail in later sections.
Figure 3
Basic T4 configuration for independent BITS/SSU output.
path8
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