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參數(shù)資料
| 型號： | PHASE-LOCKEDLOOP |
| 元件分類： | 串行ADC |
| 英文描述： | Micropower Sampling 8-Bit Serial I/O A/D Converters; Package: SO; No of Pins: 8; Temperature Range: -40°C to +85°C |
| 中文描述： | 壓控Ocillator |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 1757K |
| 代理商： | PHASE-LOCKEDLOOP |
Revision 1.01/April 2002 Semtech Corp.
Page 16
www.semtech.com
AN-SETS-7
ADVANCED COMMUNICATIONS
APPLICATION NOTE
PLL Configurations for ACS8530
The clock to the T4 feedback DFS block will have <1 ns of jitter when the T4 path is in analog feedback
mode (Reg. 35 Bit 6 = 0). However, it will have 4.9 ns when in digital feedback mode.
The TO8 output, being 64 kHz/8 kHz, can be directly divided from the clock to the T4 feedback DFS
block; therefore, it will have a similar amount of jitter on it, i.e. <1 ns when using analog feedback, and
4.9 ns when using digital feedback.
The TO9 output will have more jitter because it is synthesized from the clock to the T4 feedback DFS
block. The jitter, in addition to that present on the clock to the T4 feedback DFS block, will be equivalent
to a period of that clock, i.e. between 11 ns and 15 ns.
The jitter present on the TO9 output will range from 11 ns (when the T4 path is in DS3 mode - 89 MHz
combined with analog feedback) to 20 ns (when in 16 x E1 mode - 65 MHz combined with digital
feedback).
Appendix 1
Register definitions for configuration of the T0 and T4 paths used in the text, the default is in BOLD.
Register 35 -
cnfg_T4_Path
Bit 7
Lock_T4_to_T0
Bit selects either the T4 direct inputs, or T0 DPLL as the input of the T4 path. This allows the T4
DPLL to be used to produce different sets of frequencies to the T0 DPLL but still maintain lock.
0
T4 path locks independently from the T0 path.
1
T4 DPLL locks to the output of the T0 DPLL.
Bit 6
T4_dig_feedback
Bit to select digital feedback mode for the T4 DPLL.
0
T4 DPLL in analog feedback mode.
1
T4 DPLL in digital feedback mode.
Bit 5
Not used.
Bit 4
T4_op_from_T0
0
T08 and T09 will be generated from T4 DPLL.
1
T08 and T09 will be generated from T0 DPLL.
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