參數(shù)資料
型號(hào)： PHASE-LOCKEDLOOP
元件分類： 串行ADC
英文描述： Micropower Sampling 8-Bit Serial I/O A/D Converters; Package: SO; No of Pins: 8; Temperature Range: -40°C to +85°C
中文描述： 壓控Ocillator
文件頁(yè)數(shù)： 5/20頁(yè)
文件大?。?/td> 1757K
代理商： PHASE-LOCKEDLOOP
Revision 1.01/April 2002 Semtech Corp.
Page 5
www.semtech.com
AN-SETS-7
ADVANCED COMMUNICATIONS
APPLICATION NOTE
PLL Configurations for ACS8530
2.1
T0 DPLL Architecture and Features
The main features of the T0 DPLL are:
z
Programmable DPLL bandwidth in 18 steps from 0.5 mHz to 70 Hz.
z
Programmable damping factor for optional faster locking and peaking control. Factors = 1.2, 2.5, 5,
10 or 20.
z
Multiple phase lock detectors.
z
Phase Build-out on source switch (hitless source switching, +/- 2.5 ns).
z
Input to output Phase offset adjustment (Master/Slave), +/- 200 ns range, 6ps resolution step size.
z
Phase Build-out phase offset adjustment (source switch), +/- 3 ns range, 5ps resolution step size.
z
Detection of phase jump on the current locked to source: programmable limit from 1 - 3.5 us in 100
ms.
z
Optional automatic Phase Build-out event on a detected input phase jump.
z
Holdover frequency averaging with a choice of average times, 3rd Order anti-aliasing filter, read-out
of filtered value.
z
Low jitter MFrSync (2 kHz) and FrSync (8 kHz) outputs.
z
Revertive and non-revertive mode.
The control of the T0 DPLL is either via software or an internal state machine control. The basic
configuration for the T0 PLL is shown in Figure 2. The T0 DPLL always produces 77.76 MHz regardless
of either the reference frequency (frequency at the input pin of the device) or the locking frequency
(frequency at the input of the DPLL Phase and Frequency Detector- PFD). The input reference is either
passed directly to the PFD or via a pre-divider (not shown) to produce the reference input. The feedback
77.76 MHz is either divided or synthesized to generate the locking frequency. Digital Frequency
Synthesis (DFS) is a technique for generating an output frequency using a higher frequency system
clock. However, the edges of the output clock are not ideally placed in time, since all edges of the output
clock will be aligned to the active edge of the 204.8 MHz system clock. This will mean that the generated
clock will inherently have jitter on it equivalent to one period of the 204.8 MHz system clock.
The T0 77.76 MHz forward DFS block uses DFS clocked by the 204.8 MHz system clock to synthesize
the 77.76 MHz and, therefore, has an inherent 4.9 ns of pk-pk jitter. There is an option to use an APLL,
the T0 feedback APLL, to filter out this jitter before the 77.76 MHz is used to generate the feedback
locking frequency in the T0 feedback DFS block. This analog feedback option allows a lower jitter (<1 ns)
feedback signal to give maximum performance. The digital feedback option is present so that when the
output path is switched to digital feedback the two paths remain synchronized. The T0 77.76 MHz
forward DFS block is also the block that handles Phase Build-out and any phase offset programmed into
the device. Hence, the T0 77.76 MHz forward DFS and the T0 77.76 MHz output DFS blocks are locked
in frequency but may be offset in phase. The T0 77.76 MHz output DFS block also uses the 204.8 MHz
system clock and always generates 77.76 MHz for the output clocks (with inherent 4.9 ns of jitter). This
is fed to another DFS block and to the T0 output APLL.
The low frequency T0 LF output DFS block is used to produce three frequencies; two of them, Digital1
and Digital2, are available for selection to be produced at outputs TO1-TO7, and the third frequency can
produce multiple E1/DS1 rates via the filtering APLLs. The input clock to the T0 LF output DFS block is
either 77.76 MHz from the T0 output APLL (post jitter filtering) or 77.76 MHz direct from the T0
77.76 MHz output DFS. Utilizing the clock from the output of the APLL will result in lower jitter outputs
from the T0 LF output DFS block. However, when the input to the APLL is taken from the T0 LF output
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