參數(shù)資料
型號: PCM3006
元件分類: Codec
英文描述: 16-Bit, Single-Ended Analog Input/Output STEREO AUDIO CODEC
中文描述: 16位,單端模擬輸入/輸出立體聲音頻編解碼
文件頁數(shù): 15/16頁
文件大小: 227K
代理商: PCM3006
15
PCM3006
EXTERNAL MUTE CONTROL
Click noises are caused by DC level changes at the DAC
output. To avoid any click noises going in and out of Power-
Down Mode, an External Mute Control is generally re-
quired. The recommended control sequence is as follows:
External Mute ON, CODEC Power-Down OFF, and then,
External Mute OFF.
NOTE: If SYSCLK is stopped when the PCM3006 is in
Power-Down Mode, the device is internally reset.
THEORY OF OPERATION
ADC SECTION
The PCM3006 ADC consists of two reference circuits, a
stereo single-to-differential converter, a fully differential
5th-level delta-sigma modulator, a decimation filter (in-
cluding digital high pass), and a serial interface circuit. The
Block Diagram in this data sheet illustrates the architecture
of the ADC section, Figure 1 shows the single-to-differen-
tial converter, and Figure 10 illustrates the architecture of
the 5-level delta-sigma modulator and transfer functions.
FIGURE 9. Typical Connection Diagram for PCM3006.
FIGURE 10. Simplified 5-Level Delta-Sigma Modulator.
+
+
+
+
+
5th SW-CAP
Integrator
4th SW-CAP
Integrator
3rd SW-CAP
Integrator
2nd SW-CAP
Integrator
1st SW-CAP
Integrator
+
+
+
+
+
+
1-Bit
DAC
H(z)
Qn(z)
Analog In
X(z)
Digital Out
Y(z)
Y(z) = STF(z) X(z) + NTF(z) Qn(z)
Signal Transfer Function
Noise Transfer Function
STF(z) = H(z)/[1 + H(z)]
NTF(z) = 1/[1 + H(z)]
Comparator
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
+
4.7μF
(2)
4.7μF
(2)
+
+
+
+
1μF
(3)
1μF
(3)
Control
Interface
Audio
Interface
+3V Analog V
CC
Rch In
Lch In
SYSCLK
L/R CLK
BIT CLK
DATA OUT
DATA IN
0.1μF
and
10μF
(1)
0.1μF and 10μF
(1)
0.1μF
and 10μF
(1)
4.7μF
(4)
+
4.7μF
(4)
+
Rch Out
(5)
Lch Out
(5)
DEM0
DEM1
PDAD
PDDA
+
4.7μF
(4)
+
PCM3006
V
CC
1
V
CC
1
V
IN
R
V
REF
L
V
REF
R
V
IN
L
PDAD
PDDA
SYSCLK
LRCIN
BCKIN
DOUT
V
CC
2
NC
AGND
V
COM
V
OUT
R
V
OUT
L
DEM0
DEM1
NC
DIN
V
DD
DGND
NOTES: (1) 0.1μF ceramic and 10μF tantalum, typical, depending on power supply quality and pattern layout. (2) 4.7μF typical, gives
settling time with 30ms (4.7μF x 6.4k
) time constant in Power ON and Power-Down OFF period. (3) 1μF typical, gives 5.3Hz cut-off
frequency of input HPF in normal operation and gives settling time with 30ms (1μF x 30k
) time constant in Power ON and Power -Down
OFF period. (4) 4.7μF typical, gives 3.4Hz cut-off frequency of output HPF in normal operation and gives settling time with 47ms (4.7μF x
10k
) time constant in Power ON and Power-Down OFF period. (5) Post low pass filter with R
IN
>10k
, depending on requirement of
system performance.
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