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參數(shù)資料
| 型號(hào)： | PCM3006 |
| 元件分類(lèi)： | Codec |
| 英文描述： | 16-Bit, Single-Ended Analog Input/Output STEREO AUDIO CODEC |
| 中文描述： | 16位，單端模擬輸入/輸出立體聲音頻編解碼 |
| 文件頁(yè)數(shù)： | 13/16頁(yè) |
| 文件大小： | 227K |
| 代理商： | PCM3006 |
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13
PCM3006
SYNCHRONIZATION WITH THE DIGITAL AUDIO
SYSTEM
PCM3006 operates with LRCIN synchronized to the system
clock. PCM3006 does not require any specific phase relation-
ship between LRCIN and the system clock, but there must be
synchronization. If the synchronization between the system
clock and LRCIN changes more than 6 bit clocks (BCKIN)
during one sample (LRCIN) period because of phase jitter on
LRCIN, internal operation of the DAC will stop within 1/f
S
,
and the analog output will be forced to bipolar zero (0.5V
CC
)
until the system clock is re-synchronized to LRCIN followed
by t
DACDLY2
delay time. Internal operation of the ADC will
also stop within 1/f
S
, and the digital output codes will be set
to bipolar zero until re-synchronization occurs followed by
t
ADCDLY2
delay time. If LRCIN is synchronized with 5 or less
bit clocks to the system clock, operation will be normal.
Figures 7 and 8 illustrate the effects on the output when
synchronization is lost. Before the outputs are forced to
bipolar zero (<1/f
S
seconds), the outputs are not defined and
some noise may occur. During the transitions between normal
data and undefined states, the output has discontinuities,
which will cause output noise.
FIGURE 7. DAC Output and ADC Output for Reset and Power Down.
FIGURE 8. DAC Output and ADC Output for Loss of Synchronization.
Synchronous
Asynchronous
Synchronization
Lost
Resynchronization
within
1/f
S
Synchronous
Normal
Normal
t
ADCDLY2
(32/f
S
)
t
DACDLY2
(32/f
S
)
Undefined Data
V
(= 1/2 x V
CC
)
Undefined Data
State of
Synchronization
DAC V
OUT
Normal
Normal
(1 )
Zero
ADC DOUT
NOTES: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR
with 200ms time constant) appears initially.
Reset
Power Down
GND
V
COM
(0.5V
CC
)
Ready/Operation
Internal Reset
or Power Down
ADC DOUT
DAC V
OUT
Zero
Zero
Normal Data
(1)
t
ADCDLY1
(18432/f
S
)
t
DACDLY1
(16384/f
S
)
Reset Removal or Power Down OFF
NOTE: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR
with 200ms time constant) appears initially.
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