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參數(shù)資料
| 型號： | PCM3006 |
| 元件分類： | Codec |
| 英文描述： | 16-Bit, Single-Ended Analog Input/Output STEREO AUDIO CODEC |
| 中文描述： | 16位，單端模擬輸入/輸出立體聲音頻編解碼 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 227K |
| 代理商： | PCM3006 |
12
PCM3006
SYSTEM CLOCK
The system clock for PCM3006 must be either 256f
S
, 384f
S
or 512f
S
, where f
S
is the audio sampling frequency. The
system clock should be provided to SYSCLK (pin 9).
PCM3006 also has a system clock detection circuit which
automatically senses if the system clock is operating at 256f
S
,
384f
S
, or 512f
S
. When 384f
S
or 512f
S
system clock is used,
the clock is divded into 256f
S
automatically. The 256f
S
clock
is used to operate the digital filter and the delta-sigma
modulator.
Table I lists the relationship of typical sampling frequencies
and system clock frequencies and Figure 4 illustrates the
system clock timing.
FIGURE 5. Internal Power-On Reset Timing.
1024 System Clock Periods
Reset
Reset Removal
2.4V
2.2V
2.0V
V
DD
Internal Reset
System Clock
FIGURE 6. External Forced Reset Timing.
1024 System Clock Periods
Reset
Reset Removal
System Clock
Internal Reset
PDAD and PDDA
t
RST
PDAD = LOW and PDDA = LOW Pulse Width
t
RST
= 40ns minimum
System Clock Pulse Width High
t
SCKH
t
SCKL
12ns(min)
System Clock Pulse Width Low
12ns(min)
t
SCKH
t
SCKL
1/256f
S
,1/384f
S
,or 1/512f
S
0.7V
DD
"H"
SYSCLK
"L"
0.3V
DD
FIGURE 4. System Clock Timing.
SAMPLING RATE FREQUENCY
(kHz)
SYSTEM CLOCK FREQUENCY
(MHz)
256f
S
384f
S
512f
S
32
44.1
48
8.1920
11.2896
12.2880
12.2880
16.9340
18.4320
16.3840
22.5792
24.5760
TABLE I. System Clock Frequencies.
RESET
PCM3006 has an internal Power-On Reset circuit, as well
as an external forced reset. The internal Power-On Reset
initializes (resets) when the supply voltage V
DD
>2.0V
(typ). External forced reset occurs when PDAD = LOW or
PDDA = LOW. Figure 5 shows the internal Power-On
reset timing and Figure 6 shows the external forced reset
timing by PDAD or PDDA. During external forced reset,
the outputs of the DAC are forced to GND (see Figure 7).
The analog outputs are then forced to 0.5V
CC
during
t
DACDLY1
(16384/f
S
) after reset removal. The outputs of
ADC are also invalid, digital outputs are forced to all zero
during t
ADCDLY1
(18432/f
S
) after reset removal.
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