參數(shù)資料
型號(hào)： PCI9060SD
廠商： Electronic Theatre Controls, Inc.
英文描述： 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS
中文描述： 12O兼容的PCI總線主控接口芯片的適配器和嵌入式系統(tǒng)
文件頁(yè)數(shù)： 51/192頁(yè)
文件大?。?/td> 1551K
代理商： PCI9060SD
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)當(dāng)前第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)
SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 42
Version 1.02
in the Outbound Free List FIFO. If Outbound Free List
FIFO is not empty (head and tail pointers are not equal),
the IOP can obtain the MFA of the oldest free outbound
message frame by reading the location pointed to by the
Queue Base Register + (3 * FIFO Size) + Outbound
Free Tail Pointer Register. After the IOP reads the MFA,
it must increment the Outbound Free Tail Pointer
Register. To prevent overflow conditions, I
2
O specifies
that the number of message frames allocated should be
less than or equal to the number of entries in a FIFO.
MU also checks for overflows of the Outbound Free List
FIFO. When the head pointer is incremented and
becomes equal to the tail pointer, the Outbound Free
List FIFO is full, and the MU generates a local LSERR
(NMI) interrupt. The interrupt is recorded in the Queue
Status Control (QSR) Register.
From the time that the PCI write transaction is received
until the data is written into local memory and the
Outbound Free Head Pointer Register is incremented,
any PCI direct slave access to the PCI 9080 is issued a
RETRY.
Table 3-8. Circular FIFO Summary
FIFO
Name
PCI
Port
Generate PCI
Interrupt
Generate Local
Interrupt
Head Pointer
Maintained by
Tail Pointer
Maintained by
Inbound Free
List FIFO
Inbound Queue
Port (Host read)
No
No
Local
processor
MU hardware
Inbound Post
List FIFO
Inbound Queue
Port (Host write)
No
Yes, when Port
is written
MU hardware
Local
processor
Outbound Post
List FIFO
Outbound Queue
Port (Host read)
Yes, when FIFO
is not empty
No
Local
processor
MU hardware
Outbound Free
List FIFO
Outbound Queue
Port (Host write)
No
Yes, (LSERR) when
FIFO full
MU hardware
Local
processor
3.13.10 I
2
0 Enable Sequence
To enable I
2
O, the local processor should perform the
following:
Initialize Space 1 address and range
Initialize all FIFOs and message frame memory
Set the PCI class code in Register (PCI:09h-0Bh) to
be an I
2
O device with programming interface 01h
Set the I
2
O enable bit
Set the Local Init Done bit
Note:
NB# must be pulled up so the PCI 9080 issues
retries to all PCI accesses until the Local Init Done bit is
set in register (LOC:ECh) (refer to Table 4-59) by the
local processor.
The I
2
O enable bit in the Queue Status Register (LOC:
168h; Table 4-89) causes remapping of resources for
use in I
2
O mode. When this bit is set, all memory
mapped configuration registers (such as queue ports
40h and 44h) and Space 1 share PCIBAR0 (PCI:10h,
LOC:10h; Table 4-19). PCI accesses to offset 00h-FFh
of PCIBAR0 will result in accesses to the internal
configuration registers of the PCI 9080. Accesses above
offset FFh of PCIBAR0 will result in local space
accesses beginning at offset 100h from the Local
Space 1 Remap Register (LAS1BA, LOC:174h; Table 4-
46). Therefore space located at offset 00h-FFh from
LAS1BA is not addressable by way of PCIBAR0.
Programmer’s Note:
00h-FFh of PCIBAR0 result in internal configuration
accesses, Inbound Free MFAs must be greater than
FFh.
Because PCI accesses to offset
相關(guān)PDF資料
PDF描述
PCI950PT PC Card Support
PCI9656-AC66BI Controller Miscellaneous - Datasheet Reference
PCIB40 PC(ISA)BUS I/O CARD
PCICLOCKGEN_R001 AMD Alchemy? Solutions Au1500? PCI Clock Generation?
PCK2000 CK97 (66/100MHz) System Clock Generator(CK97 (66/100MHz) 系統(tǒng)時(shí)鐘發(fā)生器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCI9060SD-1AF 功能描述:數(shù)字總線開關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel
PCI9080 制造商:PLX 制造商全稱:PLX 功能描述:I2O Compatible PCI Bus Master I/O Accelerator Chip
PCI9080 REV3 制造商:PLX TECH 功能描述:
PCI9080-3 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI I2O Compatible PCI BUS MASTER I/O CHIP RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PCI9080-3 G 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 32Bit Master Chip RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*