參數(shù)資料
型號(hào)： PCI9060SD
廠商： Electronic Theatre Controls, Inc.
英文描述： 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS
中文描述： 12O兼容的PCI總線主控接口芯片的適配器和嵌入式系統(tǒng)
文件頁(yè)數(shù)： 100/192頁(yè)
文件大?。?/td> 1551K
代理商： PCI9060SD
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)當(dāng)前第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)
SECTION 5
PCI 9080
PIN DESCRIPTION
PLX Technology, Inc., 1997
Page 91
Version 1.02
Table 5-4. PCI System Bus Interface Pin Description
Symbol
Signal Name
Total
Pins
Pin
Type
Pin
Number
Function
AD[31:0]
Address and Data
32
I/O
TS
PCI
32-36, 39-44,
46-47, 76-81,
84-89, 91-97
All multiplexed on the same PCI pins. A bus transaction consists of an
address phase followed by one or more data phases. PCI 9080
supports both read and write bursts.
C/BE[3:0]#
Bus Command and
Byte Enables
4
I/O
TS
PCI
70-73
All multiplexed on the same PCI pins. During the address phase of a
transaction, C/BE[3:0]# defines the bus command. During the data
phase C/BE[3:0]# are used as Byte Enables. Refer to PCI spec for
further detail if needed.
CLK
Clock
1
I
54
Provides timing for all transactions on PCI and is an input to every
PCI device. PCI operates up to 33 MHz.
DEVSEL#
Device Select
1
I/O
STS
PCI
64
When actively driven, indicates the driving device has decoded its
address as the target of the current access. As an input, indicates
whether any device on the bus is selected.
FRAME#
Cycle Frame
1
I/O
STS
PCI
57
Driven by the current master to indicate the beginning and duration of
an access. FRAME# is asserted to indicate a bus transaction is
beginning. While FRAME# is asserted, data transfers continue. When
FRAME# is negated, the transaction is in the final data phase.
GNT#
Grant
1
I
51
Indicates to the agent that access to the bus is granted. Every master
has its own REQ# and GNT#.
IDSEL
Initialization Device
Select
1
I
63
Used as a chip select during configuration read and write
transactions.
INTA#
Interrupt A
1
O
OC
PCI
55
Used to request an interrupt.
IRDY#
Initiator Ready
1
I/O
STS
PCI
61
Indicates the ability of the initiating agent (bus master) to complete the
current data phase of the transaction.
LOCK#
Lock
1
I/O
STS
PCI
69
Indicates an atomic operation that may require multiple transactions
to complete.
PAR
Parity
1
I/O
TS
PCI
74
Even parity across AD[31:0] and C/BE[3:0]#. Parity generation is
required by all PCI agents. PAR is stable and valid one clock after the
address phase. For data phases, PAR is stable and valid one clock
after either IRDY# is asserted on a write transaction or TRDY# is
asserted on a read transaction. Once PAR is valid, it remains valid
until one clock after the completion of the current data phase.
PERR#
Parity Error
1
I/O
STS
PCI
65
Reporting of data parity errors during all PCI transactions, except
during a Special Cycle.
REQ#
Request
1
O
PCI
50
Indicates to the arbiter that this agent needs to use the bus. Every
master has its own GNT# and REQ#.
RST#
Reset
1
I
56
Used to bring PCI-specific registers, sequencers and signals to a
consistent state.
SERR#
Systems Error
1
O
OC
PCI
66
Reports address parity errors, data parity errors on the Special Cycle
command, or any other system error where the result will be
catastrophic.
STOP#
Stop
1
I/O
STS
PCI
62
Indicates the current target is requesting the master to stop the
current transaction.
TRDY#
Target Ready
1
I/O
STS
PCI
58
Indicates the ability of the target agent (selected device) to complete
the current data phase of the transaction.
相關(guān)PDF資料
PDF描述
PCI950PT PC Card Support
PCI9656-AC66BI Controller Miscellaneous - Datasheet Reference
PCIB40 PC(ISA)BUS I/O CARD
PCICLOCKGEN_R001 AMD Alchemy? Solutions Au1500? PCI Clock Generation?
PCK2000 CK97 (66/100MHz) System Clock Generator(CK97 (66/100MHz) 系統(tǒng)時(shí)鐘發(fā)生器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCI9060SD-1AF 功能描述:數(shù)字總線開(kāi)關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開(kāi)關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel
PCI9080 制造商:PLX 制造商全稱:PLX 功能描述:I2O Compatible PCI Bus Master I/O Accelerator Chip
PCI9080 REV3 制造商:PLX TECH 功能描述:
PCI9080-3 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI I2O Compatible PCI BUS MASTER I/O CHIP RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PCI9080-3 G 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 32Bit Master Chip RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*