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| 型號： | PCI1520-EP |
| 英文描述： | Military Enhanced Plastic PC Card Controllers Data Manual |
| 中文描述： | 軍事增強塑料PC卡控制器數(shù)據(jù)手冊 |
| 文件頁數(shù)： | 81/125頁 |
| 文件大?。?/td> | 716K |
| 代理商： | PCI1520-EP |
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4
–
28
4.39 Power-Management Control/Status Register Bridge Support Extensions
The power-management control/status register bridge support extensions support PCI bridge specific functionality.
See Table 4
–
16 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Power-management control/status register bridge support extensions
Type
R
R
R
R
R
R
R
R
Default
1
1
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Power-management control/status register bridge support extensions
A6h (functions 0, 1)
Read-only
C0h
Table 4
–
16. Power-Management Control/Status Register Bridge Support Extensions Description
BIT
SIGNAL
TYPE
FUNCTION
7
BPCC_EN
R
BPCC_Enable. Bus power/clock control enable. This bit returns 1 when read.
This bit is encoded as:
0 = Bus power/clock control is disabled.
1 = Bus power/clock control is enabled (default).
A 0 indicates that the bus power/clock control policies defined in the
PCI Bus Power Management
Interface Specification
are disabled. When the bus power/clock control enable mechanism is disabled,
the bridge power-management control/status register power state field (see Section 4.38, bits 1
–
0)
cannot be used by the system software to control the power or the clock of the bridge secondary bus. A
1 indicates that the bus power/clock control mechanism is enabled.
6
B2_B3
R
B2/B3 support for D3hot. The state of this bit determines the action that is to occur as a direct result of
programming the function to D3hot. This bit is only meaningful if bit 7 (BPCC_EN) is a 1. This bit is encoded
as:
0 = When the bridge is programmed to D3hot, its secondary bus has its power removed (B3).
1 = When the bridge function is programmed to D3hot, its secondary bus PCI clock is
stopped (B2) (default).
5
–
0
RSVD
R
Reserved. Bits 5
–
0 return 0s when read.
4.40 Power-Management Data Register
The power-management data register returns 0s when read, because the CardBus functions do not report dynamic
data.
Bit
7
6
5
4
3
2
1
0
Name
Power-management data
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Power-management data
A7h (functions 0, 1)
Read-only
00h
相關PDF資料 |
PDF描述 |
|---|---|
| PCI1620GHK | Controller Miscellaneous - Datasheet Reference |
| PCI1620PDV | Controller Miscellaneous - Datasheet Reference |
| PCI2050A | 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge |
| PCI2050GHK | BUS CONTROLLER |
| PCI2050PDV | BUS CONTROLLER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PCI1520GHK | 功能描述:外圍驅動器與原件 - PCI PC CARD CONTROLLER RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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