參數(shù)資料
型號： PCI1520-EP
英文描述： Military Enhanced Plastic PC Card Controllers Data Manual
中文描述： 軍事增強塑料PC卡控制器數(shù)據(jù)手冊
文件頁數(shù)： 109/125頁
文件大?。?/td> 716K
代理商： PCI1520-EP
5
–
22
5.20 ExCA Global Control Register
The ExCA global control register controls both PC Card sockets and is not duplicated for each socket. The host
interrupt mode bits in this register are retained for Intel 82365SL-DF compatibility. See Table 5
–
15 for a complete
description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
ExCA global control
Type
R
R
R
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
Register:
Offset:
ExCA global control
CardBus socket address + 81Eh; Card A ExCA offset 1Eh
Card B ExCA offset 5Eh
Type:
Default:
Read-only, Read/Write
00h
Table 5
–
15. ExCA Global Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
7
–
5
RSVD
R
Reserved. Bits 7
–
5 return 0s when read.
4
INTMODEB
RW
Level/edge interrupt mode select
–
card B. Bit 4 selects the signaling mode for the PCI1520 host interrupt
for card B interrupts. This bit is encoded as:
0 = Host interrupt is edge mode (default).
1 = Host interrupt is level mode.
3
INTMODEA
RW
Level/edge interrupt mode select
–
card A. Bit 3 selects the signaling mode for the PCI1520 host interrupt
for card A interrupts. This bit is encoded as:
0 = Host interrupt is edge mode (default).
1 = Host interrupt is level mode.
2
IFCMODE
RW
Interrupt flag clear mode select. Bit 2 selects the interrupt flag clear mechanism for the flags in the ExCA
card status change register (ExCA offset 04h/44h/804h, see Section 5.5). This bit is encoded as:
0 = Interrupt flags are cleared by read of CSC register (default).
1 = Interrupt flags are cleared by explicit writeback of 1.
1
CSCMODE
RW
Card status change level/edge mode select. Bit 1 selects the signaling mode for the PCI1520 host interrupt
for card status changes. This bit is encoded as:
0 = Host interrupt is edge mode (default).
1 = Host interrupt is level mode.
0
PWRDWN
RW
Power-down mode select. When bit 0 is set to 1, the PCI1520 is in power-down mode. In power-down mode,
the PCI1520 card outputs are high-impedance until an active cycle is executed on the card interface.
Following an active cycle, the outputs are again high-impedance. The PCI1520 still receives functional
interrupts and/or card status-change interrupts; however, an actual card access is required to wake up the
interface. This bit is encoded as:
0 = Power-down mode is disabled (default).
1 = Power-down mode is enabled.
相關PDF資料
PDF描述
PCI1620GHK Controller Miscellaneous - Datasheet Reference
PCI1620PDV Controller Miscellaneous - Datasheet Reference
PCI2050A 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge
PCI2050GHK BUS CONTROLLER
PCI2050PDV BUS CONTROLLER
相關代理商/技術參數(shù)
參數(shù)描述
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