參數(shù)資料
型號(hào)： PCI1520-EP
英文描述： Military Enhanced Plastic PC Card Controllers Data Manual
中文描述： 軍事增強(qiáng)塑料PC卡控制器數(shù)據(jù)手冊(cè)
文件頁數(shù)： 75/125頁
文件大?。?/td> 716K
代理商： PCI1520-EP
4
–
22
4.32 Card Control Register
The card control register is provided for PCI1130 compatibility. RI_OUT is enabled through this register, and the
enable bit is shared between functions 0 and 1. See Table 4
–
11 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Card control
Type
RW
RW
RW
R
R
RW
RW
RC
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Card control
91h
Read-only, Read/Write, Read/Clear
00h
Table 4
–
11. Card Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
7
RIENB
RW
Ring indicate output enable.
0 = Disables any routing of RI_OUT signal (default)
1 = Enables RI_OUT signal for routing to the RI_OUT/PME terminal, when RIMUX is set to 0,
and for routing to MFUNC2 or MFUNC4
6
ZVENABLE
RW
Compatibility ZV mode enable. When set, the corresponding PC Card socket interface ZV terminals enter
a high-impedance state. This bit defaults to 0.
5
PORT_SEL
RW
Port select. This bit controls the priority for the ZVSEL0 and ZVSEL1 signaling if bit 6 (ZVENABLE) is set
in both functions.
0 = Socket 0 takes priority, as signaled through ZVSEL0, when both sockets are in ZV mode.
1 = Socket 1 takes priority, as signaled through ZVSEL1, when both sockets are in ZV mode.
4
–
3
RSVD
R
Reserved. Bits 4 and 3 return 0 when read.
2
AUD2MUX
RW
CardBus audio-to-IRQMUX. When set, the CAUDIO CardBus signal is routed to the corresponding
multifunction terminal which may be configured for CAUDPWM. When both socket 0 and 1 functions have
AUD2MUX set, socket 0 takes precedence.
1
SPKROUTEN
RW
Speaker out enable. When bit 1 is set, SPKR on the PC Card is enabled and is routed to SPKROUT. The
SPKR signal from socket 0 is XORed with the SPKR signal from socket 1 and sent to SPKROUT. The
SPKROUT terminal drives data only when the SPKROUTEN bit of either function is set. This bit is encoded
as:
0 = SPKR to SPKROUT not enabled
1 = SPKR to SPKROUT enabled
0
IFG
RC
Interrupt flag. Bit 0 is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. Bit 0 is set when a
functional interrupt is signaled from a PC Card interface and is socket dependent (that is, not global). Write
back a 1 to clear this bit.
0 = No PC Card functional interrupt detected (default).
1 = PC Card functional interrupt detected.
This bit is global and is accessed only through function 0.
相關(guān)PDF資料
PDF描述
PCI1620GHK Controller Miscellaneous - Datasheet Reference
PCI1620PDV Controller Miscellaneous - Datasheet Reference
PCI2050A 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge
PCI2050GHK BUS CONTROLLER
PCI2050PDV BUS CONTROLLER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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