參數(shù)資料
型號(hào)： PCI1520-EP
英文描述： Military Enhanced Plastic PC Card Controllers Data Manual
中文描述： 軍事增強(qiáng)塑料PC卡控制器數(shù)據(jù)手冊(cè)
文件頁數(shù)： 51/125頁
文件大?。?/td> 716K
代理商： PCI1520-EP
3
–
23
NOTE 1: In the D0-uninitialized state, the PCI1520 does not generate PME and/or interrupts. When the IO_EN and MEM_EN bits (bits 0 and
1) of the command register (PCI offset 04h, see Section 4.4) are both set, the PCI1520 switches the state to D0-active. Transition from
D3cold to the D0-uninitialized state happens at the deassertion of PRST. The assertion of GRST forces the controller to the
D0-uninitialized state immediately.
NOTE 2: The PWR_STATE bits (bits 0
–
1) of the power-management control/status register (PCI offset A4h, see Section 4.38) only code for four
power states, D0, D1, D2, and D3hot. The differences between the three D3 states is invisible to the software because the controller
is not accessible in the D3cold or D3off state.
Similarly, bus power states of the PCI bus are B0
–
B3. The bus power states B0
–
B3 are derived from the device power
state of the originating bridge device.
For the operating system (OS) to manage the device power states on the PCI bus, the PCI function should support
four power-management operations. These operations are:
Capabilities reporting
Power status reporting
Setting the power state
System wake up
The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of
capabilities in addition to the standard PCI capabilities is indicated by a 1 in bit 4 (CAPLIST) of the status register (PCI
offset 06h, see Section 4.5).
The capabilities pointer provides access to the first item in the linked list of capabilities. For the PCI1520, a CardBus
bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an offset of 14h. The first
byte of each capability register block is required to be a unique ID of that capability. PCI power management has been
assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there are no more
items in the list, then the next item pointer must be set to 0. The registers following the next item pointer are specific
to the capability of the function. The PCI power-management capability implements the register block outlined in
Table 3
–
14.
Table 3
–
14. Power-Management Registers
REGISTER NAME
OFFSET
Power-management capabilities
Next item pointer
Capability ID
A0h
Data
Power-management control/
status register bridge support
extensions
Power-management control/status (CSR)
A4h
The power management capabilities register (PCI offset A2h, see Section 4.37) provides information on the
capabilities of the function related to power management. The power-management control/status register (PCI offset
A4h, see Section 4.38) enables control of power-management states and enables/monitors power-management
events. The data register is an optional register that can provide dynamic data.
For more information on PCI power management, see the
PCI Bus Power Management Interface Specification for
PCI to CardBus Bridges
.
3.8.9
CardBus Bridge Power Management
The
PCI Bus Power Management Interface Specification for PCI to CardBus Bridges
was approved by PCMCIA in
December of 1997. This specification follows the device and bus state definitions provided in the
PCI Bus Power
Management Interface Specification
published by the PCI Special Interest Group (SIG). The main issue addressed
in the
PCI Bus Power Management Interface Specification for PCI to CardBus Bridges
is wake-up from D3
hot
or D3
cold
without losing wake-up context (also called PME context).
相關(guān)PDF資料
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PCI1620GHK Controller Miscellaneous - Datasheet Reference
PCI1620PDV Controller Miscellaneous - Datasheet Reference
PCI2050A 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge
PCI2050GHK BUS CONTROLLER
PCI2050PDV BUS CONTROLLER
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