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| 型號(hào)： | PCI1520-EP |
| 英文描述： | Military Enhanced Plastic PC Card Controllers Data Manual |
| 中文描述： | 軍事增強(qiáng)塑料PC卡控制器數(shù)據(jù)手冊(cè) |
| 文件頁(yè)數(shù)： | 70/125頁(yè) |
| 文件大?。?/td> | 716K |
| 代理商： | PCI1520-EP |
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4
–
17
Table 4
–
8. System Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
31
–
30
SER_STEP
RW
Serialized PCI interrupt routing step. Bits 31 and 30 configure the serialized PCI interrupt stream signaling
and accomplish an even distribution of interrupts signaled on the four PCI interrupt slots. Bits 31 and 30 are
global to all PCI1520 functions.
00 = INTA/INTB signal in INTA/INTB IRQSER slots
01 = INTA/INTB signal in INTB/INTC IRQSER slots
10 = INTA/INTB signal in INTC/INTD IRQSER slots
11 = INTA/INTB signal in INTD/INTA IRQSER slots
Tie internal PCI interrupts. When this bit is set, the INTA and INTB signals are tied together internally and are
signaled as INTA. INTA can then be shifted by using bits 31
–
30 (SER_STEP). This bit is global to all PCI1520
functions.
When configuring the PCI1520 functions to share PCI interrupts, multifunction terminal MFUNC3 must be
configured as IRQSER prior to setting the INTRTIE bit.
Reserved. Bit 28 returns 0 when read.
P2C power switch clock. The PCI1520 CLOCK signal is used to clock the serial interface power switch and
the internal state machine. The default state for bit 27 is 0, requiring an external clock source provided to the
CLOCK terminal (terminal number F15 for the GHK package or terminal number 154 for the PDV package).
Bit 27 can be set to 1, allowing the internal oscillator to provide the clock signal.
0 = CLOCK provided externally, input to PCI1520 (default)
1 = CLOCK generated by internal oscillator and driven by PCI1520.
29
INTRTIE
RW
28
RSVD
R
27
P2CCLK
RW
26
SMIROUTE
RW
SMI interrupt routing. Bit 26 is shared between functions 0 and 1, and selects whether IRQ2 or CSC is signaled
when a write occurs to power a PC Card socket.
0 = PC Card power change interrupts routed to IRQ2 (default)
1 = A CSC interrupt is generated on PC Card power changes.
SMI interrupt status. This socket-dependent bit is set when bit 24 (SMIENB) is set and a write occurs to set
the socket power. Writing a 1 to bit 25 clears the status.
0 = SMI interrupt signaled (default)
1 = SMI interrupt not signaled
SMI interrupt mode enable. When bit 24 is set and a write to the socket power control occurs, the SMI interrupt
signaling is enabled and generates an interrupt. This bit is shared and defaults to 0 (disabled).
Reserved. Bit 23 returns 0 when read.
CardBus reserved terminals signaling. When a CardBus card is inserted and bit 22 is set, the RSVD CardBus
terminals are driven low. When this bit is 0, these terminals are placed in a high-impedance state.
0 = Place CardBus RSVD terminals in a high-impedance state.
1 = Drive Cardbus RSVD terminals low (default).
VCC protection enable. Bit 21 is socket dependent.
0 = VCC protection enabled for 16-bit cards (default)
1 = VCC protection disabled for 16-bit cards
Reduced zoomed video enable. When this bit is enabled, terminals A25
–
A22 of the card interface for PC
Card-16 cards are placed in the high-impedance state. This bit should not be set for normal ZV operation. This
bit is encoded as:
0 = Reduced zoomed video disabled (default)
1 = Reduced zoomed video enabled
Reserved. Do not change the default value.
Memory read burst enable downstream. When bit 15 is set, memory read transactions are allowed to burst
downstream.
0 = Downstream memory read burst is disabled.
1 = Downstream memory read burst is enabled (default).
Memory read burst enable upstream. When bit 14 is set, the PCI1520 allows memory read transactions to
burst upstream.
0 = Upstream memory read burst is disabled (default).
1 = Upstream memory read burst is enabled.
Socket activity status. When set, bit 13 indicates access has been performed to or from a PC card and is
cleared upon read of this status bit. This bit is socket-dependent.
0 = No socket activity (default)
1 = Socket activity
Reserved. Bit 12 returns 1 when read.
25
SMISTATUS
RC
24
SMIENB
RW
23
RSVD
R
22
CBRSVD
RW
21
VCCPROT
RW
20
REDUCEZV
RW
19
–
16
RSVD
RW
15
MRBURSTD
N
RW
14
MRBURSTU
P
RW
13
SOCACTIV
E
R
12
RSVD
R
This bit is global and is accessed only through function 0.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCI1620GHK | Controller Miscellaneous - Datasheet Reference |
| PCI1620PDV | Controller Miscellaneous - Datasheet Reference |
| PCI2050A | 32-Bit. 66MHz. 9-Master PCI-to-PCI Bridge |
| PCI2050GHK | BUS CONTROLLER |
| PCI2050PDV | BUS CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI1520GHK | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PC CARD CONTROLLER RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI1520I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:PC CARD CONTROLLERS |
| PCI1520IGHK | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PC CARD CONTROLLER RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI1520IGHKEP | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI Mil Enhance PC Card Cntrlr Data Manual RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI1520IPDV | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PC CARD CONTROLLER RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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